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Reconfigurable logic‐in‐memory device, albeit a promising hardware platform for constructing parallel computing architectures, still suffers from high power‐consumption and low area‐efficiency arising from the circuit redundancy in silicon (Si) based technical path. 2D materials are identified as potential building blocks to significantly reduce the circuit footprints with outstanding power‐efficiency, owing to their atomically thin nature and unique electronic properties. However, the present 2D logic devices are primarily based on single channel materials with homogeneous transport polarities, limiting the device reconfigurability for multi‐functional applications. Here, 2D p–n junction based dual‐gate Gaussian‐type transistors for simplified reconfigurable logic circuits are reported. All fundamental Boolean logic operators are implemented in a single device with electrically driven reconfigurability, giving rise to an ultra‐low transistor consumption down to 13% of the traditional circuits. The device is also demonstrated as a reliable image processing unit for various computing tasks (pixel processing, comparing, and ciphering) by executing the corresponding logic operations. Moreover, in situ memory of the Boolean logics is achieved by engineering the dielectric properties of the transistor without compromising its reconfigurability. These findings provide a potential approach to achieving reconfigurable logic‐in‐memory operations at the hardware level, with significant implications for the advancement of parallel computing. [ABSTRACT FROM AUTHOR]

In the article "Highly Reconfigurable Logic-In-Memory Operations in Tunable Gaussian Transistors for Multifunctional Image Processing," Du Xiang, Peng Zhou, Tao Liu, and their colleagues discuss their research on reconfigurable logic gates in Gaussian transistors. They demonstrate the use of a single Gaussian transistor to achieve in situ memory of Boolean logic gates, allowing for multiple image processing tasks. The transistor consumes only 13% of the transistor consumption of silicon-based logic circuits, making it a promising device architecture for advancing parallel computing at the hardware level. The authors of the article are Weihui Sang, Du Xiang, Yi Cao, Feixia Tan, Zichao Han, Wenyu Songlu, Peng Zhou, and Tao Liu. [Extracted from the article]