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This paper proposes a 4th-order class-AB low-pass filter (LPF) for wearable biological healthcare applications designed by cascading two 2nd-order LPFs. The proposed class-AB LPF uses quasi-floating gate (QFG), flipped source follower (FSF) and level-shifter (LS) techniques to boost its performance. The LPF is designed and validated in CMOS 180 nm technology which emulates the post-layout gain of −0.212 dB, bandwidth of 100 Hz, dynamic range (DR) of 50.26 dB, total harmonic distortion (THD) of −52.5 dB and figure of merit (FOM) of 1.71 × 10-15 J. The class-AB QFG FSF LPF consumes power and area of 0.224 nW and 0.0196 mm2, respectively. Furthermore, the statistically determined coefficient of variation for proposed LPF with 1000 iterations for gain is −0.035, THD is −0.172 and DR is 0.04, respectively. The class-AB QFG FSF LPF is compared with other LPFs which establishes its advantage in terms of low-power consumption and least figure of merit thus confirming its suitability for wearable healthcare applications. [ABSTRACT FROM AUTHOR]

This paper presents a 10 bits low-power direct digital IF to RF digital-to-analog (RF-DAC) fabricated in a 110 nm CMOS technology with a core area of 0.08 mm 2. The DAC uses sixteen current mode double balanced mixers designed without a tail transistor with different weights to convert IF output to RF output. The digital IF signal is modulated by a digital Σ − Δ modulator with 1-bit IF output. The RF-DAC with a bandwidth of 300 KHz consumes 17.3 mA from a 1.5 V supply. [ABSTRACT FROM AUTHOR]

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 μm CMOS process, the proposed LTA circuit in a two-input version consumes 3.0 μW from a 0.5 V supply and provides 10 μs crossover recovery time for a 1 pF load capacitance. [ABSTRACT FROM AUTHOR]

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell's efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at V DD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm2. The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art. [ABSTRACT FROM AUTHOR]

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]

This paper presents a performance evaluation of an ultra low-voltage non-clocked voltage comparator, designed and fabricated in a standard twin-well 130 nm CMOS technology. The comparator can handle the input voltage within rail-to-rail range and is capable of working in temperature range from −20 to 85 °C and with power supply voltage as low as 0.4 V. The comparator is intended to be employed in an on-chip energy harvester system with minimized quiescent current consumption. So-called g m / I D low-voltage design methodology in combination with the bulk-driven design approach have been selected in the circuit topology. The measurement results obtained from fabricated prototype chips, including static and dynamic parameters, are presented and discussed as well. An excellent correlation between simulations and the measured bench data has been observed with the supply voltage value of 0.6 V, while slightly less tight correlation has been reported for V DD = 0.4 V. Anyhow, simulations and measurements both confirm that the presented silicon-proven comparator topology is capable of reliable operation with power consumption within nW range. [ABSTRACT FROM AUTHOR]

Abstract This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv. [ABSTRACT FROM AUTHOR]

For the processing of signals in battery-powered and portable biological healthcare systems, there is a huge requirement for low-pass-filter (LPF) architecture. However, it's challenging to achieve low-power operation of LPF with improved figure-of-merit (FOM). This paper presents a 4th-order cascoded flipped source follower filter (CFSF) which consumes ultra-low power of 0.4 nW from 0.5 V supply. The proposed architecture has been designed in 180 nm technology using BSIM3V3 MOS models. The post-layout simulation result shows that the proposed architecture delivers a gain of −4.7 dB, bandwidth (BW) of 100 Hz, dynamic range (DR) of 57.141 dB, input referred noise (IRN) of 97 μV rms , Total harmonic distortion (THD) of −40.833 dB and FOM of 1.39 × 10−15 J. The proposed architecture occupies an area of 0.052 mm2. Further, the statistically determined values for gain, DR, and THD with 200 Monte Carlo samples indicate mean values of −7.594 dB, 48.482 dB and −48.335 dB with standard deviation values of 7.063 dB, 5.779 dB and 12.316 dB, respectively. The proposed CFSF LPF architecture can be used in portable as well as wearable biological healthcare systems. [ABSTRACT FROM AUTHOR]

• Effect of channel epilayer thickness on Analog/RF-linearity performance of a U-TFET. • Optimization of channel epilayer thickness of a U-TFET in three low-power regimes. • Impact of process-induced variation in three low-power regimes for the U-TFET. In this paper, the impact of vertical channel epilayer thickness (T epi) of a unique U-TFET has been investigated in the RF domain along with its linearity aspect. Then, a glance has been thrown to the analog domain as well. The entire study has been carried out for the three low-power performance zones. After scrutinizing the linearity vs. analog/RF performance, it has been observed that the most enhanced device in the analog/RF domain is the worst performer with respect to the linearity aspect and vice-versa. This calls for optimization. The 6-nm-T epi device turns out to be the one. Next, for the first time, a unique process-induced variation study in terms of the deviated T epi from its optimized value has been introduced to find out the degree of sensitivity of different linearity parameters with respect to the deviation. Intriguingly, no single trend has been observed in terms of the dominance of linearity parameters for the said three zones – the result remains application specific. [ABSTRACT FROM AUTHOR]

In this paper, a new high-precision, pressure sensor for sensing gas molecules using a controllable voltage-mode instrumentation amplifier (VMIA) in carbon nanotube field-effect transistor (CNTFET) technology is designed. The sensing mechanism is based on the applied force by Oxygen atoms on the surface of the carbon nanotube (CNT), which is considered as a movable electrode of sensing capacitor. The sensing mechanism is simulated in ANSYS which justifies the variations of sensing capacitance, while the sensor’s output voltage is applied to an accurate instrumentation amplifier (IA) via a switched-capacitor sensor driver. Therefore, due to the controllability of the transconductance and gain parameters of a CNTFET, the IA circuit provides a constant and controllable differential gain of up to 52 dB in a flat −3dB bandwidth of up to 3.6 MHz, which provides a tunable common-mode rejection ratio (CMRR) of up to 121 dB in a 1.8 GHz flat, −3dB frequency bandwidth. Moreover, due to the use of the differential pair stage, the total harmonic distortion (THD) value is obtained less than 0.67%. Finally, the proposed IA circuit consumes only 45.1 µW with a 22.52 nV/√Hz equivalent input referred noise value at ±0.5 V supply. [ABSTRACT FROM AUTHOR]

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans -resistance and trans -conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I a = 50 nA, I b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans -conductance (g m ) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter. [ABSTRACT FROM AUTHOR]

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18 µm standard TSMC CMOS process show that the designed comparator dissipates 135 µW of power consumption from a 1.2 V supply voltage and has the 1 mV accuracy while operating at 1 GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09 mV before and after offset cancellation, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM. [ABSTRACT FROM AUTHOR]

In this paper, using only seven MOS transistors, second order current-mode LP/BP filter is proposed. The transconductances of the MOS transistors in saturation region are used instead of passive resistors and gate-to-source capacitances are employed instead of passive capacitors. The proposed circuit exhibits important features such as simplicity, reduced chip area and wide frequency range compared to classical analog circuits that require active elements including large number of transistors. Layout of the proposed circuit is drawn using Mentor Graphics IC Station layout editor. AMS 0.35 μm process parameters are used during post-layout simulations. [ABSTRACT FROM AUTHOR]

In this paper, a fully-differential low-power low-noise neural recording amplifier with a novel recycling telescopic-cascode (RTC) operational transconductance amplifier (OTA) is presented. In the proposed RTC OTA, the current recycling and cross-coupled transistors with local positive feedback are utilized to significantly improve the OTA's parameters like small-signal DC gain and unity-gain bandwidth. The gain enhancement also improves the linearity in the closed-loop structure. Extensive analytical calculations and simulation results using TSMC 0.18-µm CMOS process are provided to examine the usefulness of the proposed OTA. The simulated neural recording amplifier achieves 3.55 µV rms input-referred noise over 1 Hz-10 kHz bandwidth with 3.03 and 1.22 noise efficiency factor for local field potential (LFP) and action potential (AP) bands, respectively. The total harmonic distortion (THD) is −41.7 dB for a 1 mV pp , 1 kHz sinusoidal input signal. The total power consumption is 1.70 µW from a single 1.8-V power supply. [ABSTRACT FROM AUTHOR]

This paper presents a new flip-flop design featuring implicit pulse-triggered structure in which a dynamic front-end stage and a static back-end one are adopted, thereby, it is considered as a hybrid flip-flop possessing both low-power and high-performance targets. Proposed flip-flop is implemented by a sampling circuit, a C-element for rise and fall paths, and a keeper stage. Simulation results in 45nm CMOS technology with a 1V supply voltage demonstrate that 27.8% and 16.9% reductions in terms of power consumption as compared to all other reported flip-flop designs in 25% and 50% data activities, respectively. Moreover, utilizing only four clocked transistors along with transition condition technique make proposed design fast and power-efficient in all activity factors, and exhibiting 5% enhancement in speed. Hence, other exploitable advantage of presented design is power-delay-product (PDPDQ) index whose improvement ranges from 16.7% to 56%. It is also indicated that presented scheme having negative setup time near zero and considrable hold time contains only 17 transistors severely affecting layout area efficiency being by as much as 12%. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance in power dissipation and PDPDQ metrics. [ABSTRACT FROM AUTHOR]

A fourth-order Σ Δ modulator (SDM) applied for micro-electro-mechanical systems (MEMS) digital geophones is presented in this paper. At the system stage, the proposed fourth-order SDM adopts a hybrid path technology including a feedforward path and a feedback path. At the design stage, a class AB operational transconductance amplifier with a gain bootstrap structure and chopper technique is employed in the first-stage integrator, which can achieve high DC gain, GBW, (Slew Rate) SR and reduce flicker noise, ensuring high (Signal-to-Noise Ratio) SNR for the proposed SDM. Meanwhile, other key modules are designed to meet basic requirements and achieve low power consumption at the same time. The proposed SDM was implemented in the SMIC 0.18 μm CMOS technology and its final area is 3.09 mm2. When the sampling frequency of 512KHz and signal bandwidth of 2KHz are adopted, the measured results show that the proposed fourth-order SDM can achieve SNR of 101 dB and ENOB of 16.4 bits with less than 5mW power consumption, which meet the requirements of high dynamic range and low power in MEMS digital geophones. [ABSTRACT FROM AUTHOR]

In this paper, a new 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology is presented. The new structure benefits from a combination of a resistor ladder and current sources. By using the resistor ladder, the identical current sources are weighted, which leads to remarkably reduce the number of current sources needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL and DNL parameters are also obtained better than 0.4 LSB. The proposed DAC dissipates just 7.49 mW power with a single supply voltage of 1.2 V. Also, the occupied area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

In this paper two reconfigurable multi band low-noise amplifiers, namely LNA1 for 802.11ah/b/g and LNA2 for 802.11ah/b/g, DCS-1800 applications using tank circuits are presented. Dual feedback is used to achieve multi band operation in both the LNAs. Power dissipation of the LNAs is reduced by employing current-reuse and forward body-biasing in the first stage of the LNAs. The novelty of the proposed approach lies in the fact that the reconfigurability of the LNAs for multi bands is achieved using simple tank circuits without requiring any additional biasing arrangement. The LNAs are designed using UMC 180 nm RFCMOS process. The post layout simulation results of LNA1 showed a power gain of 9.3 dB with noise figure of 3.7 dB, IIP3 of −2.19 dBm, DC power dissipation of 16.5 mW at 900 MHz and a power gain of 10.6 dB, noise figure of 3.1 dB, IIP3 of −2.7 dBm at 2.4 GHz. In LNA2 one common-source stage is added for further gain improvement and one more tank circuit is added to operate it additionally in GSM band, namely DCS-1800. Post layout simulation of LNA2 showed a power gain of 16.1 dB with noise figure of 4.6 dB, IIP3 of −6.57 dBm, DC power dissipation of 24.9 mW at 900 MHz; a power gain of 14.7 dB with noise figure of 5.4 dB, IIP3 of −4.34 dBm at 1.8 GHz and a power gain of 16.2 dB, noise figure of 3.6 dB, IIP3 of 0.57 dBm at 2.4 GHz. [ABSTRACT FROM AUTHOR]

• A scheme for power consumption reduction in a conventional comparator is presented. • The proposed scheme turns off the preamplifier, to reduce the power consumption. • The power-delay product is optimized using dynamic inverters. • The input referred offset is compensated using an offset cancellation scheme. Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators directly affects the overall power consumption and effective number of bits of the ADC. In this paper, an early shutdown approach is proposed to deactivate the first stage preamplifier at the suitable time. Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects. With the proposed method power consumption can be reduced in low power high precision dynamic comparators. The proposed method has been simulated in a standard 0.18 µm CMOS technology and the results confirm its effectiveness. The proposed circuit has the ability of reducing the power consumption by 21.7% in the worst case, while having little effect on the speed and accuracy in comparison with the conventional methods. The proposed comparator consumes only 47 µW while operating at 500 MHz. Furthermore, Monte Carlo evaluations showed that the standard deviation of the residual input referred offset was 620 µV. [ABSTRACT FROM AUTHOR]

In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator. At the regeneration phase, the latch is activated faster with sufficient preamplification gain and very less power consumption. Meanwhile, a cross-coupled set up of NMOS transistors in latch stage enhances the gain and speed. Unlike the previous reported comparator, the proposed dynamic circuit avoids the extra power consumption as well as delay, and establishes the optimum offset and kickback noise. The benefits in delay and power are verified with the help of analytical expressions, meticulous Monte Carlo simulations and process corner analysis in CADENCE SPECTRE at 90 nm CMOS technology. The simulation results validate that the proposed structure provides the about 2.5 times better speed and minimizes the power consumption by 3 times in comparison to hybrid double tail dynamic comparator with only 0.348 fJ/conv. energy per conversion. Moreover, it provides 2.44 mV offset with optimum kickback noise and area. [ABSTRACT FROM AUTHOR]