Search

It is attractive to design power efficient and robust SRAM in low voltage and high performance systems for mobile or battery-powered electronics. To reduce the power consumption resulting from bit-line activities, a new bit-line charge recycling circuit is proposed for 8T SRAMs. By eliminating the use of analog blocks required in existing circuits in literature, this proposed charge recycling scheme results in less design complexity. In addition, two types of SRAM cells are employed to improve the robustness in write operation, and hierarchical bit-line structure is applied to reduce the power consumption in read operation. Post-layout simulations demonstrate the proposed design results in 3.08 and 2.62 times enhancement of WSNM and SWN compared to conventional 6T SRAM design in the same technology, respectively. The power consumption of proposed design results in a reduction of 64.2% and 27.5% in write and read power consumption compared to 6T SRAM design. Moreover, given the same supply voltage (e.g., 1.2 V), post-layout simulation shows the proposed design is able to run at 5 times higher clock rate than the existing designs in literature. Given the same clock frequency requirement (e.g., 100 MHz), a lower supply voltage (e.g., 0.7 V) can sustain robust operation of the proposed design. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage and low-power CMOS precision current reference circuit, which leads to high current stability to temperature and supply variation. By exploiting the dependence of the threshold voltage and its temperature characteristics on the transistor size, a new temperature compensation method is proposed to greatly improve the temperature stability of current references and reduce its area. In addition, a novel topology is proposed to drastically enhance the supply voltage stability of current references and further improve its temperature stability. Based on a 0.18 μm standard CMOS process, post-layout simulation results show that the proposed design achieves a mean temperature coefficient (TC) of 15.71 ppm/oC over the temperature range of −20 °C to 120 °C at a 0.6 V supply voltage. The line regulation (LR) is 0.04%/V over the supply voltage range from 0.6 V to 1.8 V at 27 °C. The power consumption is 207 n W at a 0.6 V supply voltage, and the active area is 0.00808 mm2. [ABSTRACT FROM AUTHOR]

Bit line toggling of SRAM systems in write operations leads to the largest portion of power dissipation. To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit line charge. In this work, a power-efficient charge recycling SRAM is designed and implemented in 180 nm CMOS technology. Post-layout simulation demonstrates an 11% of power saving and 3.8% of area overhead, if the bit width of SRAM is chosen as 8. Alternatively, 22% of power reduction is obtained if the bit width of SRAM is extended to 64. Compared with existing charge recycling SRAM schemes, this proposed SRAM is robust to process variation, demonstrates good read/write stability, and illustrates better trade-off between design complexity and power reduction. [ABSTRACT FROM AUTHOR]