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In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

This paper proposes a novel design of an 11-transistor SRAM bit-cell with a single-ended structure and memory mini-array with the bit-interleaving architecture support using the gate-diffusion input (GDI) method based on the gate-wrap-around (GWA) CNTFETs technology. The cell core of the suggested design is composed of a robust cross-coupled structure of two asymmetric inverters based on circuit-level methodologies. The proposed bit-cell scheme exhibits significant features such as improved write-ability, read data stability, and reduced leakage/short-circuit power due to the asymmetric write-assist method and inverter gates with stacked transistors, respectively. The simulation analysis has been done based on criteria such as static noise margins (SNMs), power-delay product (PDP), and the electrical quality/yield-based figure of merits (FoMs) in write/hold/read operation cycles. The suggested SRAM bit-cell demonstrates the best results with an average of 9.36 %, 48.53 %, and 22.82 %, respectively, for FoMs against other SRAM bit-cell schemes. The Monte-Carlo simulations in the 16-nm node show better results for the proposed bit-cell in the energy and failure probability per operation cycles than similar designs, with the best performance on average of 27 % and 8 %, respectively. Finally, to investigate the effectiveness of the suggested memory cell in the real application domain, an on-chip scaled power supply memory architecture for storing digital data based on quick response (QR) code using the proposed hardware algorithm is evaluated. Our results certify that the suggested memory array configuration in comprehensive FoMs based on quality and hardware efficiency metrics shows better results than the counterpart memory architecture. [ABSTRACT FROM AUTHOR]

A compact microstrip diplexer for 4G wireless communication systems is proposed in this paper. This diplexer consists of two bandpass filters based on the triangular open loop asymmetric stepped impedance resonator in order to have a small size as well as simple structure. The T-shaped open stub is used for attenuating the undesired modes. Attenuation level for the proposed diplexer is less than 21 dB in the range of 0–10 GHz owing to using this T-shaped open stub. The center frequency of each filter can easily change in the range of 20 MHz through varying the gap length of the resonator without any changes in the whole structure of the diplexer. The result of this is the stability of other parameters like insertion loss, return loss and isolation. This diplexer has a narrow band frequency response that makes it suitable for modern wireless communication systems. Finally, the diplexer is fabricated at 2.30 and 2.55 GHz and measurements demonstrate a good agreement between simulated and fabricated diplexer. [ABSTRACT FROM AUTHOR]

In this paper a low power consumption regulator has been proposed for ultra high frequency (UHF) RFID tag that has a stable output voltage. The sub-blocks of the regulator are supplied with the elementary stage output of the rectifier. The proposed operational amplifier (OPA) circuit works in class-AB and it is biased by an adaptive biasing circuit. Besides, in the proposed regulator the used bandgap reference (BGR) circuit and the sampling circuit are based on CMOS technology and they have low power consumption. The output of this regulator is 0.81 V that has ±1.5 mV ripple. The values of LIR, PSRR and the efficiency of the regulator are about 7.5 (mV/V), 42.5 dB and 53% respectively. Considering 10 KΩ load, the power consumption of the regulator has been calculated as 147 μW. The operating frequency is 960 MHz and it is simulated in TSMC 0.18 μm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, a new compensation technique for the low noise amplifier (LNA) with the high capability and efficiency for low power applications is proposed. The supply voltage and bias of the LNA are near the sub-threshold voltage, which has excellent effect on reducing power consumption. At this voltage level, the gain decreases and the various circuit parameters become extremely sensitive to process, voltage and temperature (PVT) changes. To overcome the problem, a compensating circuit with variable current source to control the LNA bias voltage is used. The output of the compensator circuit is adjusted according to changes in temperature, voltage and five process corners, and produces a variable voltage. The temperature compensator consists of two current sources that produce a current proportional to temperature changes. Regarding process and voltage compensator, according to the state created in the circuit, the appropriate amount of current is injected through the output and finally stabilizes the main parameters of the LNA circuit. In LNA circuit, for proper performance at supply voltage near the sub-threshold and attaining the gain improvement, forward body bias and g m -boosting techniques are employed, respectively. The LNA circuit along with the PVT compensator at supply voltage of 0.35 V, consumes about 567 µW power consumption that here 91 µW is caused by the PVT compensator circuit. In the proposed circuit, the rate of noise figure (NF) and gain (S 21) changes compared to temperature changes in the five corners have decreased by 4.3 and 12.1 times versus LNA with constant bias, respectively. In this case, with 20% changes of V DD , NF and S 21 changes decreased by 23 and 11.35 times, respectively. The results are provided by Cadence software using 65 nm CMOS technology. [ABSTRACT FROM AUTHOR]

• Ultra low power and high input impedance Analog Front End for biosignals acquisition (EEG-ECG-EMG). • Design a novel structure of biomedical LNA to achieve the optimal power, noise, CMRR, and input impedance simultaneously. • Novel biomedical LNA by combining the Fully Differential Difference Amplifier (FDDA) with inverter-based. • Design a low power Programmable Gain Amplifier (PGA). In this paper, a low power and low noise analog front end (AFE) is designed for biosignal acquisition. The first stage is a low noise amplifier (LNA) that is designed by combining the fully differential difference amplifier (FDDA) structure with inverter-based to achieve the optimal power, noise, CMRR, and input impedance simultaneously. Also, to increase the output resistance of the LNA, and subsequently increase the gain without reducing the output voltage swing, the gain boosting technique has been used. To use this structure for biosignals, the second stage is designed as a programmable gain amplifier (PGA). This AFE is reconfigurable for electroencephalography (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals with variable gain of 71 dB, 56 dB, and 44 dB and bandwidth of (0.9–100 Hz), (1–560 Hz) and (12 Hz–1.5 kHz), respectively. The AFE consumes only 303 nW at 0.8 V supply voltage and confers excellent input impedance of 250 GΩ and 5.2 GΩ when the chopper is "off" and "on" respectively. The chopper method has been used and the total integrated input-referred noise is obtained, 1.4 μ V rms . The proposed AFE is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.16 m m 2. [ABSTRACT FROM AUTHOR]

In this paper, a new 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology is presented. The new structure benefits from a combination of a resistor ladder and current sources. By using the resistor ladder, the identical current sources are weighted, which leads to remarkably reduce the number of current sources needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL and DNL parameters are also obtained better than 0.4 LSB. The proposed DAC dissipates just 7.49 mW power with a single supply voltage of 1.2 V. Also, the occupied area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]