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This article presents a fully-synthesizable digital voltage regulator for applications with extremely low power consumption. The proposed design uses a synthesizable controller (DLDOC) to detect load fluctuations and control a tri-loop structural design. This tri-loop structure minimizes the ripples on output voltage (V OUT) and provides a fast-transient response (TR). This structure decreases the length of bi-directional shift register (Bi-SR) which reduces the overall power consumption. A quivering control is introduced to minimize the V OUT oscillations in steady-state. To demonstrate this design using CMOS standard-cells, a fully-synthesizable comparator (FS-comp) is utilized. A tri-state buffer array (TBA) is employed instead of conventional PMOS switch array to make this design fully-synthesizable. A pattern detection mechanism is used to switch between different loops. The proposed prototype occupies 6394 µm2 area in 45 nm CMOS technology. This design is implemented using conventional synthesis and place-and-route (P & R). For a supply voltage (VDD) of 0.5–1 V, a regulated V OUT is attained with a dropout voltage of 50 mV. At 10 MHz clock frequency, the proposed LDO achieves a quiescent current (I Q) and fast-TR of 2.2 µA and 300 ns, respectively. A maximum current efficiency (C.E.) of 99.98% is attained with output ripples < 1 mV. [ABSTRACT FROM AUTHOR]

This paper presents variable resolution SAR ADC with digitally implemented Bit enhancement logic. Unlike conventional approaches, this work avoids complex hardware architecture to reduce power consumption as the variable resolution is achieved using digitally implemented VRL (Variable Resolution Logic) block instead of combining different ADC configurations altogether. The proposed architecture utilizes the VRL block to enhance the resolution. This work first uses the linear range of an 8-bit SAR ADC as a learning dataset and then uses corresponding output bits as training data for VRL block. This VRL block further enhances the resolution with the help of a 2-bit voltage-to-digital converter by self-adjusting the required resolution after estimating the error. Less variation in sampling rate from 250 MHz to 175 MHz is achieved after implementing the VRL block. The proposed architecture is designed in 180 nm CMOS technology to validate the work. The simulation results show the ADC achieves an SNDR of 47.4 dB for 8-bit and increases to 72.11 dB for 12-bit resolution. The FoM of 253 fJ/conversion step for 8-bit SAR ADC is achieved, and it ranges from 168.3 to 35.7 fJ/conversion step in Variable resolution block phase. The area of the proposed ADC is 315.86 × 151.30 µm2. [ABSTRACT FROM AUTHOR]

A high-resolution dynamic voltage comparator with an input signal dependent power down technique for low power applications is presented here. Without affecting the resolution, a preamplifier stage has been removed from the proposed dynamic voltage comparator in order to reduce the power consumption and its delay. In this design, an input signal dependent power-down technique is used. The proposed design consists of NMOS & PMOS Input Stage Dynamic Voltage Comparator with power down (NISDVC_PD & PISDVC_PD) along with multiplexers for full rail-to-rail input swing. One out of PISDVC_PD and NISDVC_PD is active at a time to reduce power consumption. The proposed comparator has been designed using SCL 180 nm CMOS technology at 1.8 V. The simulation results of the proposed design show that the power consumption and delay is 94.1 µW and 208.28 ps at 500 MHz whereas at 2 GHz the value of the power consumption and delay is 147.7 µW and 212.5 ps, respectively. Furthermore, the offset voltage is obtained as 185.3 µV and the sensitivity of the circuit is 0.15 µV. [ABSTRACT FROM AUTHOR]

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz. [ABSTRACT FROM AUTHOR]