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Abstract This paper presents a pico-ampere voltage reference for IoT systems with high performance in line regulation and power supply rejection ratio (PSRR). Based on the leakage current characteristics of MOSFETs, the reference voltage is obtained by taking advantage of the threshold voltage differences between two types of MOSFETs with different gate oxide thicknesses. By employing a self-regulation technique, the impacts of drain-induced barrier lowering (DIBL), gate-induced drain leakage (GIDL) and gate-drain capacitance feedthrough effects can be mitigated, resulting in high performance in line regulation and PSRR. Based on a 0.18 μm standard CMOS process, post-layout simulation results show the temperature coefficient is 28.0 ppm/°C over the temperature range of 0–120 °C with a 0.6 V supply voltage. The line regulation is 2.54 ppm/V, which is at least two orders of magnitude lower than existing designs in the literature. The PSRR is −77 dB@100 Hz that is improved by at least 10 dB over existing designs in the literature. [ABSTRACT FROM AUTHOR]

As the scaling of silicon MOSFET approaches to its physical limit, research efforts have been made in exploring alternative devices. In this work, fundamental design metrics of analog circuits using two-dimensional transition metal dichalcogenide (2D-TMD) molybdenum disulfide (MoS 2 ) transistors are systematically investigated and compared with the state-of-the-art silicon MOSFETs. Based on analytical derivation and numerical simulations, we find that the drain current efficiency and channel length modulation factor of MoS 2 transistors are less relevant to the channel length. Under a condition of the same bias current and device geometry, intrinsic gains of MoS 2 transistors are at least 12.3 dB higher than silicon MOSFETs. Three case studies are performed to investigate the use of MoS 2 transistors in analog circuits. The key performance indicators of operational amplifiers, such as circuit area, power consumption, voltage gain, gain-bandwidth product (GBW), and tolerance to random process variation are studied. Simulation results demonstrate that MoS 2 based analog circuits lead to significant improvement in performance and are more resilient to process variation. For example, when designing two-stage common source amplifiers, under an iso-GBW condition, MoS 2 -based design can increase voltage gain by at least 72%, save circuit area by 45–60%, and reduce power consumption by 11–58% than silicon-based designs. [ABSTRACT FROM AUTHOR]

As the scaling of silicon MOSFET approaches to its physical limit, research efforts have been made in exploring alternative devices. In this work, fundamental design metrics of analog circuits using two-dimensional transition metal dichalcogenide (2D-TMD) molybdenum disulfide (MoS 2 ) transistors are systematically investigated and compared with the state-of-the-art silicon MOSFETs. Based on analytical derivation and numerical simulations, we find that the drain current efficiency and channel length modulation factor of MoS 2 transistors are less relevant to the channel length. Under a condition of the same bias current and device geometry, intrinsic gains of MoS 2 transistors are at least 12.3 dB higher than silicon MOSFETs. Three case studies are performed to investigate the use of MoS 2 transistors in analog circuits. The key performance indicators of operational amplifiers, such as circuit area, power consumption, voltage gain, gain-bandwidth product (GBW), and tolerance to random process variation are studied. Simulation results demonstrate that MoS 2 based analog circuits lead to significant improvement in performance and are more resilient to process variation. For example, when designing two-stage common source amplifiers, under an iso-GBW condition, MoS 2 -based design can increase voltage gain by at least 72%, save circuit area by 45–60%, and reduce power consumption by 11–58% than silicon-based designs. [ABSTRACT FROM AUTHOR]

It is attractive to design power efficient and robust SRAM in low voltage and high performance systems for mobile or battery-powered electronics. To reduce the power consumption resulting from bit-line activities, a new bit-line charge recycling circuit is proposed for 8T SRAMs. By eliminating the use of analog blocks required in existing circuits in literature, this proposed charge recycling scheme results in less design complexity. In addition, two types of SRAM cells are employed to improve the robustness in write operation, and hierarchical bit-line structure is applied to reduce the power consumption in read operation. Post-layout simulations demonstrate the proposed design results in 3.08 and 2.62 times enhancement of WSNM and SWN compared to conventional 6T SRAM design in the same technology, respectively. The power consumption of proposed design results in a reduction of 64.2% and 27.5% in write and read power consumption compared to 6T SRAM design. Moreover, given the same supply voltage (e.g., 1.2 V), post-layout simulation shows the proposed design is able to run at 5 times higher clock rate than the existing designs in literature. Given the same clock frequency requirement (e.g., 100 MHz), a lower supply voltage (e.g., 0.7 V) can sustain robust operation of the proposed design. [ABSTRACT FROM AUTHOR]

In this paper, we first investigate the noise model for 2D-TMD monolayer molybdenum disulfide ( MoS 2 ) transistors. With a proposed noise model, simulation results of low-frequency noise for MoS 2 transistors agree well with measurement data. Then, in order to evaluate potential MoS 2 -based circuits and explore design space, we utilize the behavior and noise models of monolayer MoS 2 transistors to analyze the phase noise of LC voltage controlled oscillators (LC VCOs). According to the g m / I D concept, we develop an analytical design and optimization methodology for monolayer MoS 2 based LC VCOs. For a given circuit-level design specification, the proposed design methodology can effectively balance the phase noise and current consumption. Four design examples of MoS 2 -based LC VCOs are guided using the proposed design methodology and are verified by HSPICE simulations. Compared with the HSPICE simulation results, the calculated noise phase using our proposed analytical design methodology achieves at least 95% accuracy. Finally, we design optimized LC VCO circuits with monolayer MoS 2 transistors and silicon transistors, respectively, to compare their performance. Various results reveal that the phase noise and figure-of-merit of monolayer MoS 2 -based LC VCOs are about 10 dB better than silicon-based designs. It indicates monolayer MoS 2 transistor is promising to replace silicon in analog/RF circuits for better noise performance or lower power consumption. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage and low-power CMOS precision current reference circuit, which leads to high current stability to temperature and supply variation. By exploiting the dependence of the threshold voltage and its temperature characteristics on the transistor size, a new temperature compensation method is proposed to greatly improve the temperature stability of current references and reduce its area. In addition, a novel topology is proposed to drastically enhance the supply voltage stability of current references and further improve its temperature stability. Based on a 0.18 μm standard CMOS process, post-layout simulation results show that the proposed design achieves a mean temperature coefficient (TC) of 15.71 ppm/oC over the temperature range of −20 °C to 120 °C at a 0.6 V supply voltage. The line regulation (LR) is 0.04%/V over the supply voltage range from 0.6 V to 1.8 V at 27 °C. The power consumption is 207 n W at a 0.6 V supply voltage, and the active area is 0.00808 mm2. [ABSTRACT FROM AUTHOR]

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4 K@30 fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31–64% in hardware cost. [ABSTRACT FROM AUTHOR]

Bit line toggling of SRAM systems in write operations leads to the largest portion of power dissipation. To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit line charge. In this work, a power-efficient charge recycling SRAM is designed and implemented in 180 nm CMOS technology. Post-layout simulation demonstrates an 11% of power saving and 3.8% of area overhead, if the bit width of SRAM is chosen as 8. Alternatively, 22% of power reduction is obtained if the bit width of SRAM is extended to 64. Compared with existing charge recycling SRAM schemes, this proposed SRAM is robust to process variation, demonstrates good read/write stability, and illustrates better trade-off between design complexity and power reduction. [ABSTRACT FROM AUTHOR]

This paper proposes a novel CMOS curvature-compensated bandgap reference (BGR) by using a new full compensation technique. The theory behind the proposed full compensation technique is analyzed. The proposed BGR is designed and implemented using 0.15 μm standard CMOS process. Simulation results show that the proposed BGR achieves a temperature coefficient ( TC ) of 0.84 ppm/°C over the temperature range from −40 °C to 120 °C with a 1.2 V supply voltage. The current consumption of proposed BGR is 51 μA at 27 °C. The line regulation of proposed BGR is 0.023%/V over the supply voltage range from 1.2 V to 1.8 V at 27 °C. In addition, the PSRRs of proposed BGR are −91 dB, −81 dB, −61 dB and −29 dB at DC or 10 Hz, 1 kHz, 10 kHz, and 100 kHz, respectively. [ABSTRACT FROM AUTHOR]

Based on the analysis of the limitations of traditional compensation methods for analog temperature compensated crystal oscillators (ATCXOs), a new compensation algorithm and compensation network for ATCXOs are proposed in this paper. According to the frequency-temperature characteristics of AT-cut quartz crystals, the gain-temperature characteristics of voltage control crystal oscillators (VCXOs) are firstly derived and approximated by cubic functions. To improve the gain-temperature characteristics of ATCXOs, a quartic compensation algorithm and network are derived using curve fitting technique. A proposed design is implemented using 0.40 µm BCD process. Chip measurement results show that the frequency-temperature stability is within ±0.45 ppm over a temperature range of −40 °C to 85 °C. The phase noise levels are −87 dBc/Hz, −113 dBc/Hz, −137 dBc/Hz, and −152 dBc/Hz at 10 Hz, 100 Hz, 1 kHz, and 10 kHz frequency offset of 26 MHz AT-cut crystal, respectively. Compared with existing ATCXO designs in the literature, our proposed ATCXO chip improves the frequency-temperature stability by at least 55%, while maintaining a similarly low level of phase noise. [ABSTRACT FROM AUTHOR]

This study presents a monolithic received signal strength indicator (RSSI) and an ultra-low power SAR ADC for 5.8 GHz DSRC transceiver in China electronic toll collection systems. In order to meet the stringent requirement of wide input range for the transceiver, two RSSIs collaborate with auxiliary ADC circuits to provide the digitalized received signal strength to the digital baseband of a transceiver. The RSSI design achieves fast transient response and low power consumption with a small die area by using internal active low-pass filters instead of external passive ones. The proposed design has been fabricated using a 0.13 µm 2P6M CMOS technology. Measurement results show that the overall input dynamic range is 86 dB with an accuracy of  ±1.72 dB and a transient response of less than 2 µs. Compared with the state-of-the-art designs in the literature, the overall input range and transient settling time are improved by at least 14.6%, and 300%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (K VCO ). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW. [ABSTRACT FROM AUTHOR]

This paper presents a power-switch thermal limiting technique for peak current-mode DC-DC converters to achieve maximized load current deliverability under a fixed thermal constraint. The inductor current limit of the converter is adaptively set based on the sensed switching duty-cycle to maintain a fixed power consumption limit across a wide input voltage range. The proposed current limiting circuit exhibits a fast-transient response and the chances of power-switch overheating is minimized. Since the temperature rise of the converter chip is also a function of the heat-conduction conditions such as the package type, the PCB layout, and the ambient temperature, the proposed architecture allows the power limit to be adjustable through a single off-chip resistor. Compared with a conventional switching converter which sets the inductor current limit to be constant across the entire input voltage range, the proposed approach achieves a higher available load current, especially with a higher input voltage under the same thermal constraint. In the proposed boost converter with an allowable temperature rise of 40 ° C , the proposed converter achieved 46% more available load current compared with the conventional one at the highest input voltage. [ABSTRACT FROM AUTHOR]

In a current-mode switching DC-DC converter, the amount of deliverable energy to the load depends on the inductor current limit for the safety of the power components and the slope compensation current which is determined by the slope of the inductor current and the switching duty cycle. However, excess or insufficient slope compensation current may reduce the available load current or cause subharmonic oscillations, respectively. This paper presents an input-to-output conversion ratio sensing circuit which sets a proper slope-compensation (SC) current to avoid both excess slope compensation current and subharmonic oscillations. Both the slope and the duty-cycle of the proposed slope-compensation current are automatically adjusted based on the sensed input-to-output conversion ratio. As a result, the maximum available output current and the main-loop bandwidth of the converter are improved by the proposed structure. The compensation current is generated based on a fast (<0.5 μ s settling time) sensing circuit to track the input voltage or the load current changes. The proposed slope-compensation circuit was integrated into a boost topology with 0.038 mm2 extra silicon area and 190 μ A current consumption. [ABSTRACT FROM AUTHOR]