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This paper presents a high-speed common-mode insensitive two-stage regenerative comparator designed for low supply voltage applications. The proposed comparator features a doubled transistor latch that enables rail-to-rail operation, which is pioneered to the best of the author's knowledge. The voltage swing of output nodes of the pre-amplifiers is limited to reduce the power consumption. This limitation boosts the regeneration speed of the doubled transistor latch. The proposed comparator realized by a standard 65 nm CMOS technology. The post-layout simulation results corroborate that the proposed comparator with 50 MHz sample rate and 0.6 V supply voltage dissipates 3.4 µW power, and occupies 168 µm2 area. Also, the offset voltage variation within the full common-mode range can be below 2 mV. In a worst-case scenario compared to the conventional single-stage comparator, the proposed comparator improves delay and energy efficiency by more than 80%. Considering its overall performance, this energy-efficient comparator is suitable for all low supply voltage applications, including Internet of Things (IoT), successive approximation registers analog-to-digital converters (SAR ADCs), and biomedical implants. [ABSTRACT FROM AUTHOR]

A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The proposed scheme synthesizes two reference voltages V r e f and V q to generate relevant voltage levels. The reference voltage V q is a quarter of the V r e f. To ease logic design, the V r e f is only utilized during the third phase of conversion with the MSB capacitor of each DAC. The proposed scheme reduces DAC's average switching energy and the area by 94.44 % and 50 % in comparison with the conventional single-ended scheme. Furthermore, a novel 3-stage common-mode insensitive regenerative comparator is proposed to reduce non-linearity errors caused by common-mode voltage variations of DAC. The proposed single-ended ADC is simulated in a standard 65-nm CMOS technology with a resolution of 8-bit and sampling rate of 25 MS/s. The simulation results corroborate that the ADC consumes 124 µW power with 1.2 V supply voltage and attain a 7.23 effective number of bits, resulting in a 33fJ/conversion step FOM. [ABSTRACT FROM AUTHOR]