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This paper presents static and dynamic theoretical analysis of a new Operational Transconductance Amplifier (OTA) dedicated to low-voltage and low-power applications. High linearity is obtained using signal attenuation for rail-to-rail operation. Design, layout and post-layout simulations have been carried-out with Cadence Virtuoso in a 0.18µm CMOS technology. Post-Layout Simulation (PLS) demonstrates proper operation down to ± 0.75 V supply voltage with a high open loop small-signal voltage gain of 58.26dB, a unity gain frequency of 18MHz and a total harmonic distortion of -66.55dB at 100 kHz for a peak-to-peak input voltage of 0.8V. Based on this circuit, two applications have been successfully demonstrated: on the one side, a 5th order Butterworth G mC filter and, on the other side, a voltage mode instrumentation amplifier. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices. [ABSTRACT FROM AUTHOR]

In this paper, a two-stage dynamic comparator circuit is proposed, which considerably reduces the power consumption as well as the power-delay product parameter, while improves the speed. Furthermore, the performance of the pre-amplifier stage in the proposed design is improved which properly reduces the kick-back noise as well as the power consumption. The proposed circuit operates at 1 V supply at the clock frequency of 6 GHz (high-speed scenario), which results in the static and dynamic power consumption of 112.77 nW and 848 μW, respectively. Moreover, the delay of the circuit is 36.6 ps, while the output offset voltage is only 8 mV, with the kick-back noise of 48 mV. On the other hand, the circuit can operate at 1 V supply and frequency of 500 MHz (low-power scenario), which results in the reduced static and dynamic power consumption of 112.77 nW and 188.9 μW, respectively while the offset of the circuit can be reduced to only 1 mv at the delay of 46.4 ps and kick-back noise of 39.75 mV. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of a new low-voltage and low-power OTA-C universal filter which can realise four different system topologies including: Single-Input Single-Output (SISO), Single-Input Multi-Output (SIMO), Multi-Input Single-Output (MISO) and Multi-Input Multi-Output (MIMO), without any requirement of extra switching or adding other active elements to the core filter circuit. In addition, the proposed circuit has the ability to operate in all modes of operation (multi-mode) using the grounded capacitors to effectively reduce the parasitic effects. Furthermore, to decrease the power consumption effectively, the proposed OTA-C filter is biased in the subthreshold region which significantly reduces the power consumption. Moreover, the proposed circuit has a very low sensitivity to the values of transconductance and capacitance elements. Finally, the performance of the proposed universal filter is simulated in HSPICE, using 0.18 µm CMOS technology parameters. However, the simulation results justify the design accuracy and low-power performance as well as the capability of generating filtering responses simultaneously in the different system configurations. [ABSTRACT FROM AUTHOR]

This paper presents a new low-power exponential function generator based on the first three terms of a Taylor series. This generator is used in a VGA which provides approximately 86 db of gain-range for that VGA in general. Power consumption of the exponential function generator is about (105–172) µW in maximum and minimum modes of its operation. Comparing with other reported VGAs, the whole VGA + exponential function generator + bias circuit dissipates less power which is about (576–650) µW in maximum and minimum modes of its operation. The 86 db gain-range of the VGA spans from – 24 to 62 db. This circuit and another VGA without using the exponential current have been designed in TSMC RF 0.18 μm and the results have been compared. The layout of the circuit has also been carried out in Cadence and demonstrates that the exponential function generator and the whole VGA + exponential function generator occupy 23 µm × 18 µm (0.0004 mil 2 ) and 0.0017 mil 2 of die area respectively. The post-layout-simulation of the circuit was also fulfilled and the results are displayed. [ABSTRACT FROM AUTHOR]

This paper presents a micro-watt level energy harvesting system for piezoelectric transducers with a wide input voltage range. Many such applications utilizing vibration energy harvesting have a widely varying input voltage and need an interface that can accommodate both low and high input voltages in order to harvest as much energy as possible. The proposed system consists of two rectifiers, both implemented as negative voltage converters followed by active-diodes, and three switched-capacitor DC-DC converters to either step-up or step-down and regulate to the target voltage. The system has been implemented in a 0.18 μm CMOS process and the chip measures 3 mm2. Measurements show a low voltage drop across the rectifiers and high peak power efficiency of the DC-DC converters (68.7-82.2%) with an input voltage range of 0.45-5.5 V for the complete system. Used standalone, the DC-DC converters support input voltages between 0.5 and 11 V while maintaining an output voltage of 1.8 V at an output power of 16.2 μW. The ratio of each converter is selectable to be either 1:2, 1:3, or 1:4. [ABSTRACT FROM AUTHOR]

In this paper, a low-power, low-noise and high swing capacitively coupled instrumentation amplifier for biomedical applications is proposed. It uses the folded cascode operational transconductance amplifier (FC-OTA) with current scaling at the output branch to reduce the noise. To overcome the reduction in the effective transconductance of the OTA due to current scaling, series-series and shunt-shunt feedback techniques are proposed at the folded node of the FC-OTA and the composite transistor is proposed at the bottom current source of the FC-OTA. An optimization procedure is also proposed for sizing the input transistors of the FC-OTA to obtain better noise-power tradeoff. To assess the efficacy of these techniques, a biopotential amplifier is designed in 0.18 µm CMOS process and it is studied through simulation. From this study, it is found that the proposed amplifier has a 1.5-22 times and 1.4 times higher input swing and output swing respectively compared to those reported in literature. It has a gain of 39.75 dB, a bandwidth of 0.3 Hz-4.4 kHz and a total input-referred noise of 3.19 µVrms integrated over 1 Hz-10 kHz. The power consumption of the amplifier is 4.07 µW at a VDD of 1.8 V. It achieves a noise efficiency factor of 2.78, and provides input and output signal swings of 14.86 mVpp, and 1.38 Vpp respectively at THD of 1%. [ABSTRACT FROM AUTHOR]

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation. [ABSTRACT FROM AUTHOR]

This paper presents an analog filter based on Rauch biquadratic cell. The filter exploits an improved analog stage that makes linearity performance uniform over the entire pass-band frequency region. All feedback analog filters suffer from poor linearity when the input tones frequency is in close proximity to the closed-loop poles frequency, where loop-gain reduces. This often forces an overdesign with higher current (higher power consumption) and/or higher overdrive voltages (lower dynamic range) in order to meet the linearity specifications over the whole filter pass-band region. The hereby proposed Rauch scheme resolves such a binding issue without power increasing and having the same IIP3 at low and at high frequency (up to the filter closed-loop poles frequency). Hence the linearity performance is in first approximation independent on the input tones bandwidth. In order to validate the hereby proposed idea a 4th-order 25 MHz −3 dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28 nm technology. The prototype consumes 820 µW from 1 V supply voltage and has 15 and 13 dBm IIP3 at 5 and 6 and 20 and 21 MHz input tones, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools. [ABSTRACT FROM AUTHOR]

Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient "voltage threshold adaptive memristor" model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults. [ABSTRACT FROM AUTHOR]

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input sampling and output buffer switches. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters. The simulation results confirm that the proposed S/H circuit properly operates for the data rates of higher than 2 GS/s. In addition, the proposed S/H circuit shows 14-bit resolution, 86.29 dB of SNDR for a 0.4 Vp-p, 218.75 MHz sinusoidal input signal at 2 GS/s sampling rate. [ABSTRACT FROM AUTHOR]

In this paper, the design of low-noise, low-power transimpedance amplifier (TIA) is presented for a miniaturized amperometric based continuous blood glucose monitoring system for wearable devices. The proposed multi-stage cascode common source transimpedance amplifier circuit is designed and implemented in a 180 nm CMOS technology. It has been demonstrated that the proposed TIA shows a significant increase in transimpedance gain, 1.72 GΩ with a bandwidth of 180 kHz and input referred current noise is 18 fA/√Hz for an input current of 200 pA. The total power consumption is 52 μW with a 1.4 V supply and occupies a chip area of 110 μm × 140 μm. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) without calibration based on 0.18 μm 1P6M CMOS technology. To gain one bit of resolution without increasing the number of capacitors, one-side-fixed technique is used to generate the proposed switching procedure based on merged capacitor switching (MCS) switching procedure. Besides, a new DAC control logic is proposed by inserting the SAR logic circuits into level-shift circuits to reduce the complexity of the DAC control logic, enable high-speed and low-power operation and reduce the chance of race and hazard of the combinational logic circuit at the same time. The measured results show the proposed ADC achieves an SNDR of 67.26 dB and consumes 183.3 μW at 1.8 V power supply and 2 MS/s, the peak DNL and INL are +0.66/−0.64 LSB and +0.75/−0.74 LSB, respectively, resulting in a figure-of-merit of 48.63 fJ/conversion-step. The ADC core occupies an active area of 630 × 570 µm. [ABSTRACT FROM AUTHOR]

This paper describes the design and realization of a programmable 4th-order, G-C bandpass filter for biomedical applications. The core 2nd-order filter stage is realized by a simple gyrator-C active inductor structure with a single MOSFET as the transconductor element. The capacitive input attenuation technique is used to enhance the linearity of the filter. The proposed filter was designed and simulated with a 1-V power supply voltage with process parameters from a standard 0.18 µm CMOS technology. Post-layout simulation shows that the center frequency of the filter is adjustable from 80 Hz to 6.18 kHz by using a programmable bias current generator. At a nominal center frequency of 945 Hz and the quality factor of 3, the filter exhibits a dynamic range of 57.6 dB and an input-referred noise of 174.2 µV. The filter consumes only 6 nW from a 1-V single power supply voltage and the active area of the overall circuit is 0.088 mm. [ABSTRACT FROM AUTHOR]

This paper presents power and area analysis of two-stage comb-based decimation structures for high decimation factors. The first stage is either in a recursive form cascaded-integrator-comb (CIC) or in a non-recursive form, while the second stage is in a recursive form. The proposed structures are compared with a single CIC structure. We demonstrated how to choose the decimation factor of the first stage in order to get simultaneously the highest possible power reduction and the lowest possible area increase, in a comparison with a single CIC structure. Additionally, the modified two-stage structure with an increased attenuation and a reduced power consumption is presented. Analysis is supported by MATLAB simulations and validated by the VHDL implementations. [ABSTRACT FROM AUTHOR]

The complexity of radiofrequency circuit design comes from the large number of parameters to be adjusted. Constant node shrink in CMOS process and variation of technology skills significantly contribute to this complexity. The paper reports on a reliable and portable design methodology based on a low-power figure of merit (FOM) and inversion coefficient applied to the design of a low noise amplifier (LNA). The design procedure considers the circuit specifications and the optimization of the FOM. As a case of study it is applied to 2.4 GHz LNA designed in a 28 nm technology then exploited to compare different CMOS technology nodes: 28, 65, 130 nm. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 $${\upmu }$$ W from a 800 mV power supply. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a new topology for modular frequency dividers which improves the speed and decreases the power consumption in true-single-phase-clock (TSPC) based dividers and enhances the speed in their Extended-TSPC (E-TSPC) based counterparts. Two dividers are designed in 0.18 µm TSMC CMOS technology with 1.8 V supply voltage, to examine the speed and power efficiency of proposed structure. Post-layout simulation results reveal that in TSPC based design, use of proposed structure leads to about 38 % power reduction compared to the conventional topology. In addition, the E-TSPC based design achieves the speed as high as static dividers with maintaining the programmability and modularity of divider. [ABSTRACT FROM AUTHOR]

This paper presents hybrid cascode compensation with current amplifiers (HCCCA) for nano-scale area-efficient three-stage amplifiers driving ultra-large capacitive loads. The total compensation capacitor is split and placed among two high-speed feedback loops, each with a unique current amplifier. By using HCCCA, the load-dependent non-dominant poles are pushed to much higher frequencies, thereby achieving improved performance especially for heavy capacitive loads. The employed current amplifiers make it possible to significantly reduce the physical size of the compensation capacitors and to save more silicon area. The effectiveness of the proposed technique has been verified in 90-nm CMOS process, where an HCCCA amplifier prototype is designed to drive up to 10 nF load capacitor using a compensation capacitor of only 0.5 pF. It achieves a 1.0 MHz gain-bandwidth product and 0.19 V/µs slew-rate while consuming 80 µW power from a 1.2 V supply. The achieved large-signal and small-signal performance metrics are superior to those topologies reported in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a 1.248-2.918 Gb/s low-power transmitter for MIPI M-PHY with 2-step impedance calibration loop. The voltage mode driver with the 2-step impedance calibration loop is proposed to optimize the output impedance and voltage swing. This chip is fabricated using a 0.11 μm CMOS process, and the die area is 0.385 mm. The power consumption of the transmitter is 25 mW from the supply voltage of 1.1 V. The measured RMS and peak-to-peak jitter are 4.25 and 35.24 ps in HS-G2A mode, respectively. [ABSTRACT FROM AUTHOR]

The design, implementation and testing of a wireless medical system (WMS) for continuous monitoring of biological parameters are presented in this paper. Special emphasis has been made on the implantable unit prototype. The proposed system consists of three main sections: implantable medical device (IMD), base station (BS) and graphical user interface. The IMD and BS communicate through an RF link that operates in both the industrial, scientific and medical (ISM, at 2.4-2.48 GHz) and the medical implantable communication service (MICS, at 402-405 MHz) bands. The IMD and BS are based on two commercially-available ultra-low power integrated circuits: a mixed-signal microcontroller and a medical implantable radio transceiver. A comprehensive explanation of the main design issues and implementation challenges is presented. The details regarding the analog front-end functionality, a low-power-oriented algorithm, an analysis of power consumption versus lifetime and a customized operating mode for power optimization are explained. The main considerations for link budget calculations in implantable applications are discussed. A test bench designed to emulate real conditions is used to verify the functionality of the WMS showing successful communication up to 2.1 m range with a data rate of 200 Kbps. The IMD works from a 3 V power supply with an average current consumption of 0.572 mA (including RF transmission) in continuous operation. This allows a 2 year IMD lifetime in periodic operation (for a 350 mAh battery), delivering 1 h of information per day. [ABSTRACT FROM AUTHOR]

This paper presents the design of a low-power self-compensated relaxation oscillator. The compensation does not rely on complicated circuit scheme or post-fabrication calibration but rather on the mutual compensation of the MOS transistor parameters, including threshold voltage, carrier mobility, and gate-oxide capacitance. The impacts of transistor parameters on the oscillation frequency are discussed, circuit implementation details and post-layout simulation results are also provided. This work is implemented in 0.18 μm CMOS process, only MOS transistors are used in the circuit, the chip area is 0.037 mm. Simulations show that the total power is 820 nW at the minimum supply voltage of 0.9 V, the temperature coefficient is 121 ppm/ °C in the temperature range of −40 to 85 °C, the line sensitivity is 0.33 %/V in the supply range of 0.9-2 V, the standard deviation is 2.48 % around the average frequency of 1.92 MHz. The proposed oscillator is suitable as clock generations for passive wireless systems. [ABSTRACT FROM AUTHOR]

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed 'CNFET based MCML 3 bit parity checker' exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD. [ABSTRACT FROM AUTHOR]

In this work, a new differential topology of Colpitts VCO with an enhanced transconductance is presented. The proposed circuit is consisted of an NMOS and a PMOS differential Colpitts cores configured as complementary, and also an LC resonator. The VCO is designed to oscillate at 5 GHz which consumes 1.11 VA from 1.4 V supply voltage. In addition, a modified version of the proposed VCO is designed for lower power applications. This circuit employs new positive feedbacks to enhance the VCO’s transconductance and reduce the supply voltage. The modified VCO operates with 1.1 V power supply while dissipating 1 mW. To investigate the performance of the proposed circuits, the transconductance of them are theoretically analyzed. Also, two new quadrature VCOs (QVCOs) are presented which are realized by two identical latter proposed Colpitts VCOs. A linear analysis is presented to confirm that the first oscillator can generate outputs with 90° phase differences. The proposed circuits are designed in 0.18-μm RF-CMOS technology. Finally, prototype circuits of the proposed VCOs are fabricated to validate the theoretical results. The measurement results are summarized to demonstrate the main features of the proposed oscillators. [ABSTRACT FROM AUTHOR]

A new solution for a bulk-driven ultra-low-voltage winner take all (WTA) circuit is described. The WTA structure is based on a new voltage follower (VF) circuit which could also be used in other applications as a general purpose precise VF for sub 0.5-V operation. Both proposed circuits are compact and provide precision operation confirmed by theoretical analysis. [ABSTRACT FROM AUTHOR]

The smart temperature sensor measures the room temperature and converts it to the digital domain, thus making it easier to process and store data. This work presents a fully integrated smart temperature sensor implemented in a 180 nm CMOS technology suitable for low voltage and ultra-low power electronic applications. The designed circuit uses a frequency to digital conversion topology, in which the frequency of an internal signal is linearly dependent on the room temperature. The minimum supply voltage for the designed circuit is only 0.5 V, while the occupied silicon area is 0.04 mm2. By employing a simple frequency doubler circuit and proper circuit topologies, a very low power consumption of 19 nW for a sampling frequency of 100 Hz at 27 °C is achieved. Moreover, the sensor consumes nominally 190 pJ per conversion. The simulated inaccuracy using nominal (TT) transistor models is lower than 0.5 °C over a wide temperature range of − 30 °C to 100 °C. Preliminary silicon data shows the functionality of the design circuit. Additionally, the effects of the external clock signal temperature coefficient on the performance of the designed circuit were discussed, and a correction method was proposed. [ABSTRACT FROM AUTHOR]

We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of $$0.08\,\hbox {mm}^2$$ . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is $$76\,\upmu \hbox {W}$$ from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio. [ABSTRACT FROM AUTHOR]

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer's first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm × 59 μm). [ABSTRACT FROM AUTHOR]

This work presents the design of a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and a positive feedback bulk structure. The output stage comprises a simple circuit to reduce the total voltage overhead necessary to define the logic levels. The powering scheme of the pre-amplifier, with a floating reservoir capacitor, contributes to reduce the impacts of global process variability. The positive feedback bulk structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also provides positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in a 28 nm CMOS technology and reaches an IRN below of the quantization noise of a 10 bits differential ADCs working with 600 mV power supply. The dynamic comparator achieves 237 μV input-referred noise, while consuming only 38.8 fJ per comparison and having a nominal delay of 5.77 ns. [ABSTRACT FROM AUTHOR]

Operational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultra-miniature OTAs based on non-silicon materials. During the last few years, Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) with astonishing electrical and physical properties have drawn extensive attention of nanoelectronics researchers as a potential platform to represent high-performance nanoscale OTAs. In this regard, this work aims to propose an ultra-miniature ultra-wideband OTA based on the 10 nm GAA-CNTFET technology node. The proposed OTA benefits from the ballistic transport operation of the GAA-CNTFET transistors at ultra-scaled dimensions which provide a superior bandwidth (2.88 GHz) along with suitable power consumption (44.8 μ W). The proposed OTA shows a 64.5 dB open-loop gain and a 59 dB common-mode rejection ratio at a 1 V supply voltage. Moreover, due to the utilization of the indirect feedback compensation method, the proposed GAA-CNTFET-based OTA presents an appropriate phase margin (61 ∘ ) with a smaller compensator capacitor. With the mentioned performance metrics and occupying only 0.198 μ m 2 physical area, the proposed GAA-CNTFET OTA has the potential to be considered as a replacement for nanoscale CMOS-based OTAs. [ABSTRACT FROM AUTHOR]

The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers' spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 μ W at a 1.2 V supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 μ V rms in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 mm 2 without pads. [ABSTRACT FROM AUTHOR]

A CMOS low-power 8-channel electro-encephalograph front-end circuit is presented. The single-stage instrumental amplifier in each channel employs current-reuse and chopper-stabilization technology to improve power and noise performance. An output-current-tuning ripple reduction loop (RRL) is designed to reduce the intrinsic offset of the instrumental amplifier and attenuate the chopping ripple. The proposed circuit is implemented in standard 0.18 μm CMOS process. The measured mid-band gain of the front-end is 72.5/75/78.2/81 dB and the high-pass cut-off frequency is 110/150/160/210 Hz. An input-referred noise of 0.8 μVRMS (< 100 Hz), 114 dB CMRR and 102 dB PSRR are achieved at a power consumption of 7.4 μW per channel. The proposed RRL helps to suppress the chopping ripple to a level sufficiently lower than the indigenous circuit noise. [ABSTRACT FROM AUTHOR]

This work presents a resistorless self-biased and small area sub-bandgap voltage reference that works in the nano-ampere consumption range with 0.75 V of power supply. The circuit applies a curvature compensation technique that allows an extended temperature range without compromising the temperature stability. The behavior of the circuit is analytically described, and a design methodology is proposed which allows the separate adjustment of the bipolar junction transistor bias current and its curvature compensation. Simulation results are presented for a 180 nm CMOS process, where a reference voltage of 469 mV is designed, with a temperature coefficient of 5 ppm/°C for the −40 to 125 °C extended temperature range. The power consumption of the whole circuit is 16.3 nW under a 0.75 V power supply at 27 °C. The estimated silicon area is 0.0053 mm. [ABSTRACT FROM AUTHOR]

In this work a resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results are presented for two CMOS processes, XFAB 0.18 μm and IBM 0.13 μm. Experimental results from one fabrication run demonstrate a reference voltage of 570 mV, with a temperature coefficient as low as 11 ppm/°C for the 0-125 °C range, while the power consumption of the whole circuit is 5 nW under a 0.9 V supply at 27 °C. The occupied silicon area is 0.0022 mm $$^2$$ . [ABSTRACT FROM AUTHOR]

Development of a low-power, small-size transmitter is needed for wireless sensor networks. An effective way to reduce power consumption is to reduce the operating time in a voltage-controlled oscillator. In this study, a 2.4 GHz on-off keying transmitter circuit is designed and implemented with an electrically small antenna using a left-handed transmission line. The transmitter circuit was fabricated with a standard 0.18 μm CMOS technology, while the antenna was fabricated with a 3.0 × 4.5 cm printed circuit board, chip capacitors, and chip inductors. Measured output power was −6.8 dBm with a power consumption of 3.59 mW when the baseband signal was always 'high'. The power consumption was reduced to 1.96 mW for the baseband signal with a mark ratio of 0.5. [ABSTRACT FROM AUTHOR]

A novel low voltage tunable linear transconductor is presented. The approach is based on quasi-floating gate transistors achieving higher transconductance and better dc common mode rejection than previous implementations. A dynamic biasing technique improves the sensibility of the linearity to process variations. Measurement results of the circuit, designed in a 0.5 μm CMOS process from 1.4 V power supply, confirm the advantages of the proposed approach with a very high speed operation of 50 MHz of gain-bandwidth product, a IM3 of −40 dB and a nominal power consumption of only 490 μW. [ABSTRACT FROM AUTHOR]