Search

In this work, we develop an ultrathin epitaxial h-AlN as an interfacial layer (IL) between HfO2 and monolayer WS2 channel by atomic layer deposition (ALD). The growth of ultrathin dielectrics using ALD has been challenging due to the dangling-bond-free surface of 2D materials. By utilizing sub-1 nm h-AlN as an IL and depositing HfO2 high-k dielectric, we were able to form a uniform and atomically flat gate dielectric without voids. The resulting structure exhibits an equivalent oxide thickness as low as 1 nm and ultra-low leakage currents of ∼10−6 A/cm2. The fabricated top-gate WS2 transistors demonstrate on-off ratios of around 106 and subthreshold swing as low as 93 mV/dec. Furthermore, we have verified the feasibility of using h-AlN IL for a gate-all-around structure. Our work presents a CMOS-compatible low-temperature ALD process for integrating gate dielectrics, offering excellent thickness scalability and uniform coverage around monolayer WS2 nanosheets. The combination of high-quality two-dimensional dielectrics and semiconductors will contribute to the development of future high-performance and low-power electronic devices. [ABSTRACT FROM AUTHOR]

We report on the electrical characterization of synthetic, large-area MoS2 layers obtained by the sulfurization technique. The effects of dielectric encapsulation and localized defect states on the intrinsic transport properties are explored with the aid of temperature-dependent measurements. We study the effect of dielectric environment by transferring as-grown MoS2 films into different dielectrics such as SiO2, Al2O3, HfO2, and ZrO2 with increasing dielectric permittivity. Electrical data are collected on a statistically-relevant device ensemble and allow to assess device performances on a large scale assembly. Our devices show relative in-sensitiveness of mobility with respect to dielectric encapsulation. We conclude that the device behavior is strongly affected by several scattering mechanisms of different origin that can completely mask any effect related to dielectric mismatch. At low temperatures, conductivity of the devices is thermally activated, a clear footprint of the existence of a mobility edge separating extended states in the conduction band from impurity states in the band-gap. [ABSTRACT FROM AUTHOR]

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs. [ABSTRACT FROM AUTHOR]

Conventional junctionless (JL) multi-gate (MuG) field-effect transistors(FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. [ABSTRACT FROM AUTHOR]