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Ultrathin SiO2 grown by plasma-assisted oxidation (plasma oxide) has been investigated by high-resolution x-ray photoemission spectroscopy and medium energy ion scattering spectroscopy. We found that the plasma oxide grown at the low temperature of 400°C has a thinner transition layer than conventional thermal oxide. This thinner transition layer in the plasma oxide not only decreased the gate leakage current effectively, but also enhanced the reliability of the gate oxide. We attribute these electrical properties of the plasma oxide to the reduction of the transition layer.

Negative bias-induced instability of amorphous hafnium indium zinc oxide (α-HIZO) thin film transistors (TFTs) was investigated at various temperatures. In order to examine temperature-induced effects, fabricated TFTs with different combinations of gate insulator and gate metal were stressed by a negative gate bias at various temperatures. As a result, it is proved that negative bias-induced hole-trapping in the gate insulators and temperature-enhanced electron injection from the gate metals occurs at the same time at all temperatures, and the instability of HIZO TFT is more affected by the dominant factor out of the two mechanisms.

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

Bipolar ac stress-induced instability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors is comparatively investigated with that under a positive dc gate bias stress. While the positive dc gate bias stress-induced threshold voltage shift (ΔVT) is caused by the charge trapping into the interface/gate dielectric as reported in previous works, the dominant mechanism of the ac stress-induced ΔVT is observed to be due to the increase in the acceptorlike deep states of the density of states (DOS) in the a-IGZO active layer. Furthermore, it is found that the variation of deep states in the DOS makes a parallel shift in the IDS-VGS curve with an insignificant change in the subthreshold slope, as well as the deformation of the CG-VG curves.