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Ultra-thin barrier (UTB) 4-nm-AlGaN/GaN normally-off high electron mobility transistors (HEMTs) having a high current gain cut-off frequency (fT) are demonstrated by the stress-engineered compressive SiN trench technology. The compressive in-situ SiN guarantees the UTB-AlGaN/GaN heterostructure can operate a high electron density of 1.27 × 1013 cm−2, a high uniform sheet resistance of 312.8 Ω/□, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ SiN in the 600-nm SiN trench, the short-gated (70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode (E-mode). Meanwhile, the novel device also can operate a large current of 610 mA/mm and a high transconductance of 394 mS/mm for the E-mode devices. Most of all, a high fT/fmax of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode AlGaN/GaN HEMTs. Besides, being together with the 211 GHz/346 GHz of fT/fmax for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of fmax over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E- and D-mode designs the addition of the SiN trench, will promise an enormous competitive advantage in the fabricating costs. [ABSTRACT FROM AUTHOR]

The graded AlGaN:Si back barrier can form the majority of three-dimensional electron gases (3DEGs) at the GaN/graded AlGaN:Si heterostructure and create a composite two-dimensional (2D)–three-dimensional (3D) channel in AlGaN/GaN/graded-AlGaN:Si/GaN:C heterostructure (DH:Si/C). Frequency-dependent capacitances and conductance are measured to investigate the characteristics of the multi-temperature trap states of in DH:Si/C and AlGaN/GaN/GaN:C heterostructure (SH:C). There are fast, medium, and slow trap states in DH:Si/C, while only medium trap states exist in SH:C. The time constant/trap density for medium trap state in SH:C heterostructure are (11 μs–17.7 μs)/(1.1 × 1013 cm−2·eV−1–3.9× 1013 cm−2·eV−1) and (8.7 μs–14.1 μs)/(0.7× 1013 cm−2·eV−1–1.9× 1013 cm−2·eV−1) at 300 K and 500 K respectively. The time constant/trap density for fast, medium, and slow trap states in DH:Si/C heterostructure are (4.2 μs–7.7 μs)/(1.5× 1013 cm−2·eV−1–3.2× 1013 cm−2·eV−1), (6.8 μs–11.8 μs)/(0.8× 1013 cm−2 · eV−1–2.8× 1013 cm−2 · eV−1), (30.1 μs–151 μs)/(7.5× 1012 cm−2 · eV−1–7.8× 1012 cm−2 · eV−1) at 300 K and (3.5 μs–6.5 μs)/(0.9× 1013 cm−2 · eV−1–1.8× 1013 cm−2 · eV−1), (4.9 μs–9.4 μs)/(0.6× 1013 cm−2 · eV−1–1.7× 1013 cm−2 · eV−1), (20.6 μs–61.9 μs)/(3.2× 1012 cm−2 · eV−1–3.5× 1012 cm−2·eV−1) at 500 K, respectively. The DH:Si/C structure can effectively reduce the density of medium trap states compared with SH:C structure. [ABSTRACT FROM AUTHOR]

A high performance InAlN/GaN high electron mobility transistor (HEMT) at low voltage operation (6–10 V drain voltage) has been fabricated. An 8 nm InAlN barrier layer is adopted to generate large 2DEG density thus to reduce sheet resistance. Highly scaled lateral dimension (1.2 μm source–drain spacing) is to reduce access resistance. Both low sheet resistance of the InAlN/GaN structure and scaled lateral dimension contribute to an high extrinsic transconductance of 550 mS/mm and a large drain current of 2.3 A/mm with low on-resistance (Ron) of 0.9 Ω⋅mm. Small signal measurement shows an fT/fmax of 131 GHz/196 GHz. Large signal measurement shows that the InAlN/GaN HEMT can yield 64.7%–52.7% (Vds = 6–10 V) power added efficiency (PAE) associated with 1.6–2.4 W/mm output power density at 8 GHz. These results demonstrate that GaN-based HEMTs not only have advantages in the existing high voltage power and high frequency rf field, but also are attractive for low voltage mobile compatible rf applications. [ABSTRACT FROM AUTHOR]

We investigate the instability of threshold voltage in D-mode MIS-HEMT with in-situ SiN as gate dielectric under different negative gate stresses. The complex non-monotonic evolution of threshold voltage under the negative stress and during the recovery process is induced by the combination effect of two mechanisms. The effect of trapping behavior of interface state at SiN/AlGaN interface and the effect of zener traps in AlGaN barrier layer on the threshold voltage instability are opposite to each other. The threshold voltage shifts negatively under the negative stress due to the detrapping of the electrons at SiN/AlGaN interface, and shifts positively due to zener trapping in AlGaN barrier layer. As the stress is removed, the threshold voltage shifts positively for the retrapping of interface states and negatively for the thermal detrapping in AlGaN. However, it is the trapping behavior in the AlGaN rather than the interface state that results in the change of transconductance in the D-mode MIS-HEMT. [ABSTRACT FROM AUTHOR]

The etch-stop structure including the in-situ SiN and AlGaN/GaN barrier is proposed for high frequency applications. The etch-stop process is realized by placing an in-situ SiN layer on the top of the thin AlGaN barrier. F-based etching can be self-terminated after removing SiN, leaving the AlGaN barrier in the gate region. With this in-situ SiN and thin barrier etch-stop structure, the short channel effect can be suppressed, meanwhile achieving highly precisely controlled and low damage etching process. The device shows a maximum drain current of 1022 mA/mm, a peak transconductance of 459 mS/mm, and a maximum oscillation frequency (fmax) of 248 GHz. [ABSTRACT FROM AUTHOR]

In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal--insulator--semiconductor (MIS) high electron mobility transistors (HEMTs), we demonstrate better performances of recessed-gate Al2O3 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine-based AlGaN etching with three etching times (15 s, 17 s and 19 s). The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of AlGaN/GaN HEMT. Through the recessed-gate etching, the transconductance increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with tit = (0.20[?]1.59) us and Dit = (0.55[?]1.08) x 1012 cm[?]2 * eV[?]1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AlGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time (15 s in this paper) can enhance the performances of MIS-HEMTs effectively. [ABSTRACT FROM AUTHOR]

An enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMTs) was fabricated with 15-nm AlGaN barrier layer. E-mode operation was achieved by using fluorine plasma treatment and post-gate rapid thermal annealing. The thin barrier depletion-HEMTs with a threshold voltage typically around [?]1.7 V, which is higher than that of the 22-nm barrier depletion-mode HEMTs ([?]3.5 V). Therefore, the thin barrier is emerging as an excellent candidate to realize the enhancement-mode operation. With 0.6-um gate length, the devices treated by fluorine plasma for 150-W RF power at 150 s exhibited a threshold voltage of 1.3 V. The maximum drain current and maximum transconductance are 300 mA/mm, and 177 mS/mm, respectively. Compared with the 22-nm barrier E-mode devices, VT of the thin barrier HEMTs is much more stable under the gate step-stress. [ABSTRACT FROM AUTHOR]