Search

A novel low specific on-resistance (Ron,sp) lateral double-diffused metal oxide semiconductor (LDMOS) with a buried improved super-junction (BISJ) layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage (BV). The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively. [ABSTRACT FROM AUTHOR]

A novel silicon controlled rectifier (SCR) with high holding voltage ( for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (, the two SCRs are turned on at the same time to induce the first snapback with high (. As the increases, the SCR2 will be turned off because of its low current gain. Therefore, the will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high (. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized of 7.4 V with a maximum failure current ( of 14.7 mA/ is obtained by the simulation. [ABSTRACT FROM AUTHOR]

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer. [ABSTRACT FROM AUTHOR]

A low specific on-resistance SOI LDMOS with a novel junction field plate (JFP) is proposed and investigated theoretically. The most significant feature of the JFP LDMOS is a PP—N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buried oxide layer (BOX) and thus widens the vertical conduction area. As a result, the breakdown voltage (BV) is improved and the specific on-resistance (Ron,sp) is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ·cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices. [ABSTRACT FROM AUTHOR]

An analysis model of the dV/dt capability for a metal—oxide—semiconductor (MOS) controlled thyristor (MCT) is developed. It is shown that, in addition to the P-well resistance reported previously, the existence of the OFF-FET channel resistance in the MCT may degrade the dV/dt capability. Lower P-well and N-well dosages in the MCT are useful in getting a lower threshold voltage of OFF-FET and then a higher dV/dt immunity. However, both dosages are restricted by the requirements for the blocking property and the forward conduction capability. Thus, a double variable lateral doping (DVLD) technique is proposed to realize a high dV/dt immunity without any sacrifice in other properties. The accuracy of the developed model is verified by comparing the obtained results with those from simulations. In addition, this DVLD MCT features mask-saving compared with the conventional MCT fabrication process. The excellent device performance, coupled with the simple fabrication, makes the proposed DVLP MCT a promising candidate for capacitor discharge applications. [ABSTRACT FROM AUTHOR]