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An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a digital circuit designer. Most of the times, the designer sacrifices power consumption and chip area to decrease delay for a given technology node. To overcome this problem, we propose the ternary threshold logic gate. We have implemented the proposed gate by combining the threshold logic with the ternary logic. Then, we have constructed basic building blocks of a ternary ALU (as ternary logic gates, comparator, and arithmetic circuits) using the proposed ternary threshold logic gate. We have compared these building blocks and implemented with the proposed gate, with the ones implemented using different technologies. Via simulations, we have shown that the proposed gate may be utilized to decrease delay, power consumption, and chip area of ternary circuits. Thus, the proposed ternary threshold logic gate can be used to decrease delay, power consumption, and chip area of ternary circuits. [ABSTRACT FROM AUTHOR]

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs. [ABSTRACT FROM AUTHOR]

An energy-efficient, low-noise, and high-speed dynamic comparator is proposed in this work. The comparator uses two pre-amplifiers to have a two-stage operation for reduced kickback noise. It also incorporates the adaptive current reuse (ACR) technique for reduced latency and high-speed operation. The proposed comparator is designed and simulated in a 65-nm UMC CMOS process using a 1.2-V power supply. The performance of the design is verified using post-layout simulation and also through Monte Carlo simulations. The resultant offset standard deviation of 8 mV is observed, which is 3 times less compared to the conventional design. The maximum operating frequency of the comparator is 1 GHz. The worst-case energy consumption is 67 fJ with an average latency of 70 ps. The kickback noise of 5.5 mV is observed for the entire working range, which is almost 10 times less compared to the conventional dynamic comparator at 500 MHz clock frequency. [ABSTRACT FROM AUTHOR]

An artful complex algorithm to achieve high-efficiency high-precision multiobjective synchronous modeling and optimal solving of an analog IC is proposed. The complete approach combines response surface methodology (RSM) with an improved support vector regression (SVR) machine, which shows obvious superiority in nonlinear modeling and global solution by reduced training datasets. Targeting an analog comparator circuit as the experimental object, 33 sets of optimal design parameters are solved first in the RSM preprocessing stage, and these high-quality sample data can be subsequently input to the SVR machine for model training. In the second SVR solving stage, a differential evolution (DE) algorithm is adopted to further auto-optimize the modeling factors of the SVR machine to improve the accuracy of the nonlinear model. Finally, an SVR model of the comparator circuit can be obtained to accurately describe the response relationships of performance metrics and the corresponding design parameters that are expected by designers. With the comparator design based on TSMC 65 nm/1.2 V standard CMOS technology, we compare the SVR model-based prediction value with the Cadence-based simulation result by design test-bench and observe error lower than 3%. This work proved that the proposed complex RSM-DE-SVR algorithm is significantly practical and effective to benefit the aided optimization design of analog ICs. [ABSTRACT FROM AUTHOR]

A coarse-fine tuning technique with analog enhancement (AE) operation is proposed for the digital low-dropout (DLDO) regulator. Once the undershoot or overshoot is detected, the coarse tuning quickly finds out the coarse control loop in which the load current should be located, with large power PMOS size and high sampling frequency. Then, the fine tuning, with reduced power PMOS size and sampling frequency, regulates the DLDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. By using time-domain comparator instead of voltage-domain comparator, the voltage signal is converted to time signal and the comparison result is obtained through phase discriminator to identify phase difference, so that DLDO can realize low-voltage operation. Meanwhile, the AE operation is introduced to reduce the overshoot/undershoot voltage by increasing the transient current of the power PMOS. The proposed DLDO is designed using a 180 nm 1P6M CMOS process with a 0.09 mm2 active area. The post-simulated undershoot and overshoot voltages are only 50.26 and 34.66 mV, respectively, when the load current changes between 1 and 2.5 mA, and the maximum recovery time is 305.3 ns. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

An on-chip nanopower RC relaxation oscillator is developed in a 180-nm standard CMOS process, consuming 300 nW while running at 10 kHz. Employing a frequency compensation scheme that reduces the frequency drift introduced by comparator offset and delay, the proposed oscillator achieves a significant low temperature coefficient. Furthermore, a supply regulation structure is used to reduce the frequency sensitivity to supply voltage variations. Post-simulation results show that the frequency variation against temperature is 105 ppm/ ∘ C in the temperature range from 0 to 85 ∘ C, and the line sensitivity is 2.19%/V with the supply voltage changing from 1.05 to 1.45 V. At offset frequencies of 100 Hz and 1 kHz, the simulated phase noises are −50 and −71 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

Reconfigurability is an important capability that provides flexibility in computing architecture and low-power technique. It is challenging in digital-in-concept for designing smart analog circuits operated on low power. This work presents a low-power, low-noise, and high-speed multistage feed-forward reconfigurable comparator for medium-to-high-speed analog-to-digital converter. A power-efficient reconfigurable comparator design at 180 nm is presented with a new power reduction and offset compensation technique. The proposed dynamic latch-based 2-stage comparator gives an 83.2% power saving compared with a 3-stage comparator. The reduced number of active stages in comparator lowers the load capacitance to the post-amplifier and the power consumption. The 2-stage comparator gives a high slew rate, low power consumption, and better result at a Nyquist rate of 2.4 GS/s as compared with the previous state of the art. We have also proposed the reconfigurable multistage comparator, which gives the features of both 2-/3-stage comparators. We have performed the post-layout simulation to validate the design for process variation and mismatch with proposed circuit and compared with state of the art. Further, the voltage gain is 100 dB with power supply 1.8 V while consuming 523.4 μ W and 86.15 μ W for 3-stage and 2-stage comparator, respectively. [ABSTRACT FROM AUTHOR]

Using multi-valued logic (MVL) can reduce chip connections, which can have a direct effect on the chip area and connections power consumption. In the recent years, due to the high capability of nanotechnology in designing MVLs, some researchers have focused on this field. In designing MVL circuits, the low-complexity design is of great importance to fulfill the MVL aim. In this paper, a very low-complexity comparator for the MVL is proposed based on the multi-threshold voltage in CNTFETs. The proposed comparator in the 1-bit greater function only needs four transistors for all multi-valued logics; this results in a considerable transistor count reduction in comparison with the pervious works relying on 32 and 50 transistors in a ternary to quaternary case, respectively. Also, the number of 1-bit comparators is reduced from 50 and 74 transistors for the ternary to quaternary cases in the previous works to 12 in the proposed design. Additionally, the multi-digit comparator using the novel digit comparator is proposed. The simulation results using the Stanford 32 nm CNTFET library in HSPICE confirm the proper operation of the proposed comparator with the same range in PDP, in comparison with the previous works. [ABSTRACT FROM AUTHOR]

In this paper, an active CMOS rectifier with new delay compensation technique for wireless power transmission system is proposed. In order to reduce the delays of the comparators employed in the proposed rectifier, a new low-power common-gate comparator is proposed which presents higher speed compared with the conventional counterpart. Moreover, a negative feedback loop changes the bulk voltage of PMOS transistors in the comparator to compensate the remaining turn-off delay of the circuit and its variation against all process, voltage, and temperature variations. Therefore, due to the reduction in the delay and consequently the reverse current of the active diodes, power conversion efficiency and voltage conversion ratio (VCR) of the proposed rectifier are increased considerably. Besides, since the feedback signal is applied to the bulk terminal of transistors in the comparator, it does not need any extra circuitry for generating the required offset current. The proposed circuit is simulated in a standard 0.13-µm CMOS technology. Post-layout simulation results show that, with ± 1.2 V input amplitude, the proposed circuit presents a maximum efficiency of 86.7% with 200 Ω loading, a peak VCR of 97%, and a minimum voltage ripple of 6.5 mV with 2 kΩ loading. [ABSTRACT FROM AUTHOR]

Due to high-speed and low area, domino circuits are used in a variety of applications such as comparator, adder, MUX, memory, microprocessor, and adder. In this paper, we propose a keeper controlling network to improve the noise immunity and performance for wide fan-in OR footless domino circuit. In the proposed design, the keeper controlling network controls the keeper transistor. The network itself consists of an NMOS transistor, which acts as a switch and inverter chain. This network turns OFF the keeper transistor at the start of evaluation phase to enhance the speed of the domino circuit. Similarly, it turns ON the keeper transistor, when all inputs are at low voltage in the evaluation phase to enhance the noise immunity. We simulate the proposed design and other existing circuits using 90 nm CMOS technology on HSPICE. The simulation results show that the proposed design considerably reduces delay, power consumption, power delay product, and improves unity noise gain as compared to the HS-domino circuit for 32-inputs OR gate. [ABSTRACT FROM AUTHOR]

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]

In this work, we propose a novel procedure to generate and select threshold inverter quantized (TIQ) comparators for TIQ Flash ADCs. The new procedure generates more TIQ comparators than the procedure designed by Lee , Yoo, and Choi (LYC) (Proceedings of International Symposium on Quality Electronic Design, 2002). Two 6-bit TIQ Flash ADCs were designed, the LYC flash ADC, which selects its TIQ comparators using the current threshold selection algorithm, and the AC TIQ Flash ADC, which selects its TIQ comparators using the threshold selection algorithm proposed herein. Both ADCs were designed in $$0.5\,{\upmu }\hbox {m}$$ CMOS technology and compared against the process, voltage source, and temperature (PVT) variations. Proposed TIQ selection procedure allows the designer to select the optimum TIQ set for desired ADC. AC ADC has a DNL values ±0.015 LSB and INL values between $$\pm 0.0225$$ compared to ±0.1 LSB and 0.3 to −0.1 LSB for DNL and INL values of the LYC ADC. ENOB and SNDR for the AC were improved by at least $$31.3\%$$ compared to LYC ADC, at typical process settings. For process, voltage source, and temperature (PVT) variations, in overall the AC ADC has at least better the DNL values by at least $$22.5\%$$ and reduced INL values by at least $$35\%$$ . Over PVT variation, AC ADC has maintained ENOB value greater than 5.3 bits for all 16 variation corners. ENOB was improved by at least 1.5 bits over all corners. SNDR and SFDR were increased by at least 4 dB over the PVT corners. Proposed AC procedure shows scalability feature by generating extra threshold points for the $$65\hbox {-nm}$$ TIQ comparators. [ABSTRACT FROM AUTHOR]

In applications related to human senses, such as audio and image processing, computations with limited precision are acceptable. In these areas, a digital system can be implemented using approximate computing that works with sufficient precision. In this paper, we present a method to design 2-bit approximate magnitude comparators that are effectively low cost in terms of power, area and speed. We build larger comparators with adjustable error characteristics. Compared to precise one, our approximate comparators can save power and area up to 7-46 % and 10-50 %, respectively. The structures of our comparators and their error characteristics are presented in this paper. We use these comparators to design different approximate image median filters in order to remove salt and pepper noise. Simulation results show that the output quality of these filters is very similar to that of the precise ones so that the degradation is not noticeable. The approximate filters save up to 30 % of power and area while working 18 % faster than the precise ones. [ABSTRACT FROM AUTHOR]

Comparators are the main components in several analog and mixed-signal systems. Design and synthesis of comparator architectures largely remain an analog designer's art. In this work, we present a systematic methodology for designing comparators using the method of constrained optimization. Constrained optimization is an equation-based optimization method and requires accurate equations. We propose a new delay equation for latch-based comparators. The new delay model is based on Adomian decomposition method and gives more accurate delay characteristics compared with the conventional one. The architecture is optimized for total power dissipation with speed, area and noise as the constraints. Geometric programming-based automation algorithm and the behavioral model of the comparator architecture are written in MATLAB. The optimized schematic is drawn in Cadence 180 nm technology, and the results are verified with MATLAB. [ABSTRACT FROM AUTHOR]

A Hamming distance comparator (also known as $$k$$ -order comparator) compares its two operands and outputs an agreement if they differ in less than $$k$$ corresponding bits. In this paper, we introduce novel architectures for the design of Hamming distance $$k$$ comparators, for the usually adopted values 2 or 3 for $$k$$ . The proposed architectures are fully digital and are based on splitting the difference vector in smaller groups and performing comparison against $$k$$ in parallel with counting, leading to significant speedup against previous proposals. The derived architectures can also be used for fixed-threshold Hamming weight comparators for small or large threshold values. The proposed 2- and 3-order comparators are more than 60 and 31 % more efficient than the most competitive previous proposal, respectively, using the area $$\times $$ time $$^2$$ metric, while their total power dissipation remains low. [ABSTRACT FROM AUTHOR]