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Focuses on the efforts of the Institute of Electrical and Electronics Engineers (IEEE) and the Open Verilog International (OVI) committee to develop analog extensions to VHDL and Verilog. Verilog-A's use of a probe/source model; Difficulty involved in simulating complex circuits in the early stages of the design process; Features of available analog simulators. INSET: Postscript..

Reports that the VHDL initiative toward application specific integrated circuit (ASIC) libraries (VITAL) has become an Institute of Electrical and Electronics Engineers (IEEE) standard. Background on VITAL; Iterations made before the IEEE 1176.4 specification was passed; Availability of products to generate VITAL libraries.

Reports on developments related to hardware-description languages (HDL). Market data from Electronic Design Automation Cos.; Proponents of the VHDL and Verilog languages.

Reports on Analogy Inc.'s planned announcement of the availability of an analog/digital simulator based on the VHDL/VHDL-A 1076.1 hardware description language. Disadvantages of the backplane technology; Importance of the VHDL/VHDL-A standard on unified language.

Reports on Computer Aided Software Technologies's announcement of a library of VHDL computer language models that can run on PCS microcomputers and UNIX workstations. Features and pricing of the models.

Provides information on digital signal processing (DSP) and VHDL-analog-mixed-signal (AMS) design. Levels of structural modeling where analog refers to transistors and logic refers to gates; Need for maintenance of key historical languages.

Announces Chrysalis Symbolic Design's VHDL language support for its formal verification products. Chrysalis' suite of formal tools use for verifying designs; Availability of Chrysalis products.

Reports on the effects of the `Portable Library Rationalization' efforts of Meta-Software's Kima Hailey on the creation of analog extensions to VHDL and Verilog computer hardware description languages.

Reports on verification and testing tools for application specific integrated circuit (ASIC)-based systems. Synopsys' VHDL System Simulator; VEDA Design Automation's VerdictFault VHDL fault simulator; Development plans.

Discusses why analog-computer users should start learning to write equations for behavioral models in the light of the IEEE 1076.1 standard analog VHDL versions presented by San Jose, California-based Cadence Design Systems and Ulm, Germany-based Anacad EES GmbH. Dangers of a non-standard version of analog VHDL; Documentation; Cadence's reason for shipping its analog VHDL.