Search

In this work, the influence of Hf cap thickness of bipolar resistive switching in TiNHfO2HfTiN resistive random access memory (RRAM) stack was investigated. More stable bipolar switching and longer endurance were achieved by increasing the Hf cap thickness from 2nm to 10nm. First-principle simulation suggested more oxygen vacancies (Vox) generation for thicker Hf cap. Lower FORMING voltage from thicker Hf cap devices confirms more Vox generation in the stack. X-ray photoelectron spectroscopy (XPS) also physically detected more oxygen scavenge from HfO2 bulk by thicker Hf cap. The more generated Vox in thicker Hf cap stack probably accounted for the improved bipolar switching properties.

This paper gives an overview of the different trends and challenges of fully Si-based and hetero-junction tunnel field effect transistors (TFETs). The different horizontal and vertical approaches are discussed in view of processing aspects and device performance. A benchmarking is given of the state-of-the-art experimental data reported in the literature, enabling to highlight the potentials of these emerging devices.

We explain the basic operation of a nanowire pinch-off FET and graphene nanoribbon tunnelFET. For the nanowire pinch-off FET we construct an analytical model to obtain the threshold voltage as a function of radius and doping density. We use the gradual channel approximation to calculate the current-voltage characteristics of this device and we show that the nanowire pinch-off FET has a subthreshold slope of 60 mV/dec and good ION and ION/IOFF ratios. For the graphene nanoribbon tunnelFET we show that an improved analytical model yields more realistic results for the transmission probability and hence the tunneling current. The first simulation results for the graphene nanoribbon tunnelFET show promising subthreshold slopes.

Tunnel-FETs (TFETs) have the potential for a subthreshold swing below 60 mV/dec such that supply voltage scaling beyond the 1 V plateau of metal-oxide-semiconductor FETs (MOSFETs) is possible. The latter scaling is a necessary condition for a reduction of the power consumption per transistor. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon results in low on-currents. Therefore, the incorporation of heterostructures is proposed. In particular, a germanium-source silicon-channel n-TFET and, as complementary p-TFET, an indium(gallium)arsenide-source silicon-channel TFET reach on-currents comparable to MOSFETs. TFETs offer new opportunities, like the short-gate configuration, due to their different operating principle. At the same time, the latter implies that models need to be newly developed. The agreement of models with experimental data is still qualitative only.

In this paper we review some advances in High-k characterization by means of capacitance measurement in the radio-frequency regime (widely known as RFCV). Firstly, we present a robust methodology for the gate impedance parameter extraction in short channel leaky devices, based on measurements from DC to the GHz range and fitting with a robust weighted algorithm. Secondly, we will present a novel RFCV technique which pushes the conventional split-CV measurement to the MHz range. This RF-split-CV is based on measuring with a 2-port network analyzer, as opposed to the conventional technique which uses a 1 port LCR meter. This improved technique is the basis for accurate mobility extraction as studied in the final part of the paper. This methodology takes parasitics fully into account: the RF-split-CV curves obtained are used for the accurate metallurgical channel length extraction. Combination of these Lmet results with conventional Ids Vgs curves measured in the linear regime leads to the source and drain resistance calculation. After all these corrections have been performed, the mobility is finally calculated.

To control gate leakage current, Hf-based dielectrics have been selected for replacing SiON. Hf-stacks generally suffer from more defects than SiO2. This work reviews the latest progress in the understanding of these defects and compares them with those in SiO2. Attention will be focused on the stress-induced negative charging and the process-induced positive charging. On the negative charging, difficulties for characterizing the highly unstable trapping in thin Hf-layers will be tackled. Key trap properties are determined, including capture cross sections, effective density and spatial location. It is found that the capture cross section of as-grown electron traps in Hf-stacks is similar to that of generated electron traps in SiO2. On process-induced positive charges, it will be shown that Hf-stacks and SiO2 also have common features, including a large sample-to-sample variation, mobile and fixed charges, and stability. Overall, Hf-stacks, especially nitrided, behave like an inferior or stressed SiO2.

An asymmetric shift of the capacitance-voltage characteristics of n-Ge/Si/SiOx/HfO2/TaN p-FET is reported, namely a shift of the threshold voltage (Vth) towards positive values in inversion, while the flat-band voltage (Vfb) remains constant. First-principles calculations on silicon-passivated germanium surfaces reveal the formation of a dipole layer at the Ge/Si interface, which leads to a decrease of the substrate work-function/threshold voltage by 0.5-0.6V. Silicon-induced surface states are also found in the germanium band-gap. When the substrate Fermi level is located near these states, electrons are transferred to the silicon layer and compensate the work-function shift, explaining the absence of Vfb shift. We propose a possible remedy for this asymmetry by inverting the strain at the Ge/Si interface. The growth of Si/strained- Ge/Si layers reduces the interface dipole and cleanses the electronic gap from interface states. The combination of these two factors is expected to restore the symmetry between Vth and Vfb.

Recently germanium MOSFETs have attracted attention due to the promising carrier mobility of germanium compared to silicon. To understand the germanium MOSFET interface, the conductance interface trap density extraction technique was verified for the first time on germanium MOSFETs. In order to know the characteristics of the (near-) interface traps it is essential to confirm the validity of the model on which their extraction is based. It cannot be simply assumed that the interface will behave as in Si. For this purpose low temperature measurements were performed at 80 K and a variation on the ac conductance technique was developed. Typical Si impedance behavior is found for Ge but Si extraction methods cannot be applied to Ge capacitors in general. Indications for weak Fermi-level pinning near the conduction band were found in Si-passivated Ge/HfO2 capacitors. This explains the weak performance of the corresponding nMOSFET.

In this work, the influence of Hf cap thickness of bipolar resistive switching in TiNHfO2HfTiN resistive random access memory (RRAM) stack was investigated. More stable bipolar switching and longer endurance were achieved by increasing the Hf cap thickness from 2nm to 10nm. First-principlesimulation suggested more oxygen vacancies (Vox) generation for thicker Hf cap. Lower FORMING voltage from thicker Hf cap devices confirms more Voxgeneration in the stack. X-ray photoelectron spectroscopy (XPS) also physically detected more oxygen scavenge from HfO2bulk by thicker Hf cap. The more generated Voxin thicker Hf cap stack probably accounted for the improved bipolar switching properties.

CARBonCHIP ("Carbon Nanotubes Technology on Silicon Integrated Circuits") has been a three year EU FP6 STReP collaborative project aimed to determine whether carbon nanotubes are a viable material to be used in the manufacture of interconnected transistors for future electronic devices beyond the 22 nm node. The research activities performed within the CARBonCHIP consortium primarily focused on the back end of line leading to the ability to now selectively grow dense bundles of vertical CNTs (10E12 CNTs cm-2) inside small diameter vias (140 nm) with repeatable yield. The final project deliverable, summarised in this paper, has been the generation of a materials based roadmap indicating further development of CNTs as a viable building block in nanoelectronics IC devices to extend Moore's Law beyond the year 2020. As this is a public report, only information which has been published or disseminated at a public level is being documented.