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Reports on the upcoming technology of Blue Pearl Software Inc. that will identify and fix functional and design-for-test errors in RTL code, locate false paths and automatically generate timing constraints for synthesis. Collaboration of the company with Veritable Inc.; Significance of the collaboration for the expansion of Veritable's technology into the tool markets; Upcoming tools Blue Pearl will address.

This article focuses on SystemVerilog hardware description and verification language introduced as of December 15, 2003. The language has far broader capabilities, more complex syntax and a whole new learning curve. It is designed to be fully backward-compatible with Verilog language, while incorporating a host of new features by means of technology donations from such companies as Co-Design Automation Inc., Synopsys Inc., Verplex Systems and Intel Corp. Management will enjoy the productivity benefits of a common language for design and verification. The complex transition from system model to implementation will be greatly eased.