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The appearance of quantum computing in the short foreseeable future and its capability to break conventional cryptographic algorithms forces to change the paradigm of secure real‐time communications. Thus, government organizations, data centers, and enterprises among others are migrating their public key infrastructure towards using post‐quantum cryptography (PQC) algorithms in order to mitigate the security threats posed by quantum computers. This letter presents the first quantum resilient secure end‐to‐end communication link based on PQC algorithms operating between two data‐processing units DPU. Both data‐processing units employ on‐board ARM processors to perform the computationally expensive cryptographic building blocks—in that case CRYSTALS‐Kyber as a key encapsulation mechanism and CRYSTALS‐Dilithium for digital signature scheme in combination with advanced encryption standard with 256‐bit key. [ABSTRACT FROM AUTHOR]

A large number of studies are there for Advanced Encryption Standard (AES) fault attack analysis, but less for fault recognition. This paper presents a recognition method for single‐byte fault which is induced in the last three rounds of AES. Studying the differential characteristics of Sbox, the single byte fault induced in ninth round or tenth round will be identified respectively with 9.3 and 9.1 ciphertexts. For the fault induced in eighth round, the fault value can be obtained with 188.5 ciphertexts by analyzing the differential features of two Sboxes and MixColumns. As an auxiliary means for fault attacks, this method is used to realize the byte or bit level physical positioning of confidential data in the encryption chip, which is beneficial to reduce the blindness of the attacker's experiments and obtain the sensitive area of fault attack. [ABSTRACT FROM AUTHOR]

Fault attack is a type of active attack which retrieves the secret key by injecting computational faults. Laser is one of the most common fault injection methods. When attacking substitution‐permutation networks‐ciphers, S‐box is often chosen as the laser injection target. However, the adversary has to know whether the S‐box is corrupted or not after each injection, which was difficult in real‐world attacks. Two analysing methods to distinguish the S‐box faults for different ciphers is proposed in this Letter. A laser‐based physical experiment is carried out to verify the authors' methods on Advanced Encryption Standard and PRESENT ciphers on an ATmega163L microcontroller. Experimental results show that their methods can precisely distinguish S‐box faults merely using dozens of ciphertexts. [ABSTRACT FROM AUTHOR]

The design of ultra‐low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2‐Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1‐Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent. [ABSTRACT FROM AUTHOR]

In this Letter, an efficient implementation of the bit‐parallel polynomial basis (PB) multiplier over the binary field GF(28) generated by the type I irreducible pentanomial f(y) = y8 + y4 + y3 + y + 1 is presented. This pentanomial is especially important because it is used in the advanced encryption standard (AES). Therefore, any optimisation of the multiplier complexity over this finite field is very relevant because efficient AES implementation can be obtained. The bit‐parallel multiplier here presented has the lowest delay known to date for similar multipliers based on this irreducible pentanomial. [ABSTRACT FROM AUTHOR]

A power analysis attack countermeasure, called power‐awareness‐based hiding, is proposed. It is effective in implementing nonlinear operations, S‐boxes, in cryptographic algorithms. An advanced encryption standard (AES) S‐box circuit has been implemented in this approach using the Domino logic array style. The post‐layout simulation results show that the power‐aware hiding AES S‐box achieves a delay of 1.56 ns and a mean power consumption of 3.57 mW. The proposed method improves the power delay product by 65%, the normalised energy deviation by 43% and the normalised standard deviation by 30% compared to other secure methods. [ABSTRACT FROM AUTHOR]

Fault attack is a type of active attack which retrieves the secret key by injecting computational faults. Laser is one of the most common fault injection methods. When attacking substitution-permutation networksciphers, S-box is often chosen as the laser injection target. However, the adversary has to know whether the S-box is corrupted or not after each injection, which was difficult in real-world attacks. Two analysing methods to distinguish the S-box faults for different ciphers is proposed in this Letter. A laser-based physical experiment is carried out to verify the authors' methods on Advanced Encryption Standard and PRESENT ciphers on an ATmega163L microcontroller. Experimental results show that their methods can precisely distinguish S-box faults merely using dozens of ciphertexts. [ABSTRACT FROM AUTHOR]

A deep learning (DL)-assisted and combined side-channel attack (SCA) is exploited to disclose the secret key of an advanced encryption standard (AES) cryptographic circuit with a countermeasure. Different physical leakages of the protected AES cryptographic circuit such as power dissipation and electromagnetic (EM) emission are captured together at first. Then the deep neural networks are utilised to model the relationship between the power noise and the EM noise by analysing the captured power dissipation and EM emission profiles. Ultimately, a special power attack is performed on the protected AES cryptographic circuit to leak the secret key efficiently through using the EM noise to filter the power noise. As demonstrated in the results, for the conventional SCAs, the secret key of the protected AES cryptographic circuit is undisclosed to the adversary even if 1 million plaintexts are enabled. By contrast, only analysing 32,500 number of plaintexts are sufficient to leak the secret key if the DL-assisted and combined SCA is executed. [ABSTRACT FROM AUTHOR]

A masked advanced encryption standard (AES) physical unclonable function (PUF) architecture is proposed for hardware authentication against hybrid side-channel (SCA) and machine-learning attacks (MLAs). The random mismatches of the load capacitance of the masked substitution-boxes in the AES cryptographic circuit induced by the fabrication process are utilised for generating the critical-authentication data against SCAs. Moreover, a mask data is added to the input challenge data to mask the actual input data of the proposed PUF against MLAs. As demonstrated in the results, the masked AES PUF proposed shows a nearly 51.1% uniformity, 50.7% inter- Hamming distance, and 98.1% reliability. Furthermore, if a hybrid SCA/MLA is performed on the proposed PUF by combining the corresponding side-channel leakage with the deep neural network algorithm, the prediction rate of the output responses of the masked AES PUF is only 55.2% after 100,000 number of challenge-to-response pairs are used for training. [ABSTRACT FROM AUTHOR]

The article offers information on a deep learning (DL)-assisted and combined side-channel attack (SCA) method produced by the researchers from the Old Dominion University and the University of Minnesota Twin Cities for improving the cryptographic circuit secret key of an advanced encryption standard (AES) efficiencies. It mentions about the use of cryptographic circuits for encrypting processors and Internet of Things (IoT) devices.