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A testable design for detecting stuck-at and bridging faults in programmable logic arrays (PLAs) based on double fixed-polarity Reed–Muller (DFPRM) expression is presented. DFPRM expression has the advantage of compactness and easy testability. The EXOR part in the proposed structure is designed as a tree of depth (⌈log2s⌉+1), where s is the number of product terms and sum terms in the given DFPRM expression realised by PLAs. This solves an open problem of designing an EXOR-tree-based RMC network that admits a universal test set. For an n-variable function, a test sequence of length (2n+8) vectors is sufficient to detect all single stuck-at and bridging faults in the proposed design. The proposed EXOR-tree-based network reduces circuit delay significantly compared with cascaded EXOR-based design. The test sequence is independent of the function and the circuit-under-test, and the test set can be stored in a ROM for built-in-self-test. [ABSTRACT FROM AUTHOR]

Testable designs of GRM (generalised Reed-Muller) and ESOP (EXOR sum-of-products) circuits have been proposed for robustly detecting all single stuck-open faults in their CMOS implementation. It is shown that for an n-variable boolean function, a sequence of (4n + 13) vectors is sufficient to detect all single stuck-open faults in a GRM circuit. For an ESOP circuit, a test sequence of length (2n + 10) is sufficient. In the first case, the EXOR part is designed as a tree of depth ≤ 2(log [p + 1]), and for the latter, as a linear cascade of length ≤ (p + 1), where p is the number of product terms in the GRM or ESOP expression. For both the cases the test sequence is universal, i.e. independent of the function and the circuit under test, and can be stored in a ROM for built-in self-test. [ABSTRACT FROM AUTHOR]