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Ge MOS devices passivated by SmGeOx with equivalent oxide thickness of 0.61 nm were employed as the platform to evaluate the eligibility of SmGeOx as Ge surface passivation layer. The SmGeOx layer was formed by deposition of Sm2O3 on Ge substrate with a subsequent O2 annealing and the formation of SmGeOx was confirmed by X-ray photoelectron spectroscopy. The tiny frequency dispersion in capacitance measurement and a low interface trap density of 5.1\times 10^11~cm^-2eV^-1 near midgap attest to desirable passivation effect and it can be ascribed to Sm-Ge-O bonding, which is favorable in mitigating dangling bonds at Ge surface. In addition, the small hysteresis in capacitance also suggests good quality of bulk dielectric. Due to the small amount of bulk traps and large conduction band offset with respect to Ge, it enjoys low leakage current of 0.36 A/cm^2 at gate bias of Vfb (flatband voltage)-1 V. Through the test of bias temperature instability, the passivation layer demonstrates reasonable reliability performance in terms of 65-mV flatband voltage shift at 85^\circC after stressing with -16~MV/cm for 1000 s. With these characteristics, SmGeOx is promising as a passivation layer for aggressively scaled Ge MOS devices. [ABSTRACT FROM AUTHOR]

TaN/ZrTiOx/Pt metal-insulator-metal structure was employed as the platform to evaluate the eligibility for antifuse one-time programmable (OTP) memory applications, and the impact of O2 plasma on device performance was also discussed. Owing to the oxygen radicals that enhance the dielectric integrity, the voltage for state switching increases with O2 plasma treatment. Memory cells without plasma treatment demonstrate promising characteristics for OTP memory applications in terms of a low dc switching voltage of 2 V, high programming speed of 60 ns, high read endurance up to 10^6 reading cycles, and desirable retention time and low switching power density of 6.4 mW/cm^2. The memory cell technology not only exhibits the prominent performance which is advantageous over other dielectrics reported in the literature, but it also possesses the capability to from stackable 3-D architecture. [ABSTRACT FROM PUBLISHER]

Perovskite-based BaZry\rm Ti1-y\rm O3 (BZTO) (y=0.6) with partial crystallization has been found to possess a rather high-\kappa value of 48.6 and positive quadratic voltage coefficient of capacitance (VCC). Through stacking BZTO and ZrTiOx as laminate dielectric, metal–insulator–metal capacitors using VCC canceling effect advance frontiers by exhibiting a record-low VCC of 14 ppm/V^2 at the capacitance of 13.4 fF/\mum^2, low dielectric loss tangent <0.01, and low leakage current of 7.5\times 10^-9~A/cm^2 at -1~V. With constant voltage stress at 2.5 V for 1000 s, degradation in leakage current <30\% is observed. In addition, excellent reliability of 0.89% capacitance change against stress up to a projected of 10 years is also achieved. The aforementioned characteristics not only compare favorably to other high-\kappa-based dielectrics, most importantly, but also these results meet ITRS requirements set by 2024. [ABSTRACT FROM AUTHOR]

In this letter, ZrLaOx/\rm ZrTiOx/ZrLaOx laminate is employed as the platform for investigating the effects of plasma nitridation on the electrical performance and reliability of metal–insulator–metal capacitors. After plasma nitridation of ZrTiOx, the capacitance density and quadratic voltage coefficient of capacitance (VCC-\alpha) degraded slightly to 14.38 fF/\mum^2 and 68 ppm/V^2. These results meet the International Technology Roadmap for Semiconductors requirements for implementation in 2020. The major benefits of plasma nitridation are the enhanced performance of the electrical characteristics and reliability. The process reduces leakage current by a factor of 32.8, and improves stress-induced leakage current by a factor of 10.6. In addition, near frequency-independent capacitance is achieved after stressing at 2.5 V for 1000 s, and a desirable reliability of 0.27% capacitance change after a 10-year operation under 2.5-V stress is attained. These results suggest that nitrided ZrTiOx enables ZrLaOx/\rm ZrTiOx/ZrLaOx laminate to be a candidate for use in advanced circuit applications. [ABSTRACT FROM PUBLISHER]

Metal–insulator–metal (MIM) capacitors with \ZrLaOx \/ZrTiOx\/ZrLaOx laminate as the insulator were explored in this work. Single \ZrTiOx dielectric was found to have a negative quadratic voltage coefficient of capacitance (VCC-\alpha) with a high \kappa value of 22.5. By integrating this dielectric with \ZrLaOx which provides a positive VCC- \alpha and a high \kappa value of 25.8, the “canceling effect” of VCC- \alpha can be achieved while a high capacitance density can be maintained. MIM capacitors with the laminated structure display desirable characteristics in terms of a capacitance density of 14.6 \fF/\mu\m^2, a low VCC- \alpha of 33 \ppm/V^2, negligible frequency dispersion, and satisfactory leakage current of \1.6 \times \10^-6\ \A/cm^2 at -1.5 V. These results also well meet the International Technology Roadmap for Semiconductors requirement set for 2020. [ABSTRACT FROM AUTHOR]

Resistive random access memory (RRAM) cells with a thin oxygen-deficient \ZrTiOx film topped by a Ti oxygen-gettering layer and a Pt electrode were fabricated on n-Ge layer, and the switching mechanism, as well as electrical characteristics, was explored. The RRAM cells demonstrate a stable bipolar switching behavior without the requirement of a forming process. Because of the existence of a larger amount of interface traps which would trap carriers and help build a favorable electric field for the drift of oxygen vacancies, the RRAM cells possess lower SET and RESET voltages compared to those fabricated on n-Si layer. With many promising properties such as a large sensing margin of 300 times, a high operation speed of 250 ns, a robust endurance of \10^5\ \cycles, and a long data retention time of up to 10 years, the \ZrTiOx-based RRAM cells exhibit a promising perspective as nonvolatile memory devices for Ge-based technology. [ABSTRACT FROM AUTHOR]

Because of a higher permittivity than \Al2\O3, a large conduction band offset and high thermal stability, a thin amorphous \Yb2\O3 layer was integrated with a \ZrTiO4 film as the gate stack for advanced Si MOS devices. With 800 ^\circ\C annealing, the \ZrTiO4 film can be crystallized in orthorhombic phase with permittivity of 45.9 and a gate stack with equivalent oxide thickness of 0.86 nm can be achieved. This crystalline \ZrTiO4/\Yb2\O3 gate stack demonstrates negligible frequency dispersion in capacitance, low interface trap density of \1.86 \times \10^11\ \cm^-2\eV^-1 , leakage current of \6.7 \times \10^-6\ \A/cm^2 at gate bias of flatband voltage (VFB)-1\ \V, and high extrapolated 10-year lifetime operating voltage of -2.9 V. These promising electrical characteristics suggest that the crystalline \ZrTiO4/\Yb2\O3 gate stack holds great potential to be applied to aggressively scaled CMOS technology. [ABSTRACT FROM AUTHOR]

Metal–insulator–metal (MIM) capacitors with crystalline- \TiO2/\SiO2 stacked dielectric are explored in this letter. The crystalline \TiO2 possesses a high permittivity while the \SiO2 provides a negative quadratic voltage coefficient of capacitance (VCC\-\alpha) to cancel out the positive VCC\-\alpha from the crystalline \TiO2. These desirable properties render MIM capacitors with high performance in terms of a capacitance density of 11.9 \fF/\mu\m^2 with a VCC\-\alpha of 90 \ppm/V^2. With additional \N2 plasma treatment on the crystalline \TiO2, because of the effective passivation of grain-boundary-related defects and, consequently, a lower leakage current by a factor of 50, the VCC\-\alpha can be further lowered to 30 \ppm/V^2 with slight degradation in capacitance density to 11.2 \fF/\mu\m^2, which well meets the requirement in 2018 set by ITRS. [ABSTRACT FROM PUBLISHER]

Metal-insulator-metal (MIM) capacitors with single \TiO2 and a \TiO2/\Y2\O3 stack as an insulator are explored in this letter. It is found that, at the process temperature higher than 400 ^\circ\C, \TiO2 MIM capacitors demonstrate a high capacitance density at the price of an unacceptably high leakage current and voltage coefficient of capacitance (VCC). On the other hand, with the process temperature of 500 ^\circ\C, \TiO2/\Y2\O3 MIM capacitors display desirable characteristics in terms of a large capacitance density of 32.2 \fF/\mu\m^2, a low VCC of 3490 \ppm/ \V^2, small frequency dispersion, and a low leakage current of \4.5\! \times\! \10^-9\ \A/\cm^2 at -1 V. The \Y2 \O3 film not only provides a high dielectric–electrode band offset but also possesses high thermal stability against crystallization; both are important to suppress leakage current. In addition, the \Y2\O3 film prevents a \TiO2 film from crystallization at 500 ^\circ\C due to the increased entropy caused by incorporated Y atoms, and the amorphous \TiO2 film offers a high \kappa value to achieve a large capacitance density without sacrificing leakage current and VCC. [ABSTRACT FROM AUTHOR]

\SnGeOx films formed by thermal oxidation of Sn/Ge and \SnGex/\Ge structures were confirmed by X-ray photoelectron spectroscopy and explored to investigate the capability of passivation for Ge MOS devices. It is found that Sn incorporation into germanium oxide is effective in suppressing the formation of volatile GeO. For \SnGeOx films formed by oxidation of \SnGex/\Ge structures, due to fewer dislocations between \SnGex and Ge, it enjoys an interface trap density of \2.1 \times \10^11\ \cm^-2 \cdot \eV^-1, which is lower than those oxidized from Sn/Ge structures. Furthermore, the films also demonstrate desirable electrical characteristics in terms of tiny frequency dispersion and small hysteresis in capacitance measurement, a low leakage current of \9.3 \times \10^-10\ \A/cm^2 at a gate voltage of -1 V with an effective oxide thickness of 3.6 nm, and a good bias temperature instability of 15-mV flatband voltage shift at 85 ^\circ\C after 12.5 MV/cm stress for 1000 s. [ABSTRACT FROM AUTHOR]