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To improve the electrical performance of thin-film transistors with an atomic-layer-deposited Al2O3 dielectric/InOx channel, O2 plasma surface treatments of the InOx back channel are explored in comparison with thermal annealing. It is demonstrated that the O2 plasma treatment can enhance the device performance much more efficiently than thermal annealing, exhibiting an extremely low-thermal budget. Furthermore, it is revealed that the plasma treatment at a higher temperature can improve the device performance much faster than that at a lower temperature. For a 4 min O2plasma treatment at 200 °C, superior electrical characteristics are achieved, such as a field-effect mobility of 11 cm2V−1s−1, a threshold voltage of 0.9 V, a subthreshold swing of 0.38 V/dec, and good gate bias stress stabilities. This is ascribed to faster passivation of oxygen vacancies, removal of more C residues, and weaker surface damage and smaller surface roughness of the InOx back channel in comparison with long plasma treatments at lower temperatures.

Memristor-based logic operation has attracted a lot of interest ever since the material implication and NAND logic operations were successfully implemented with several memristive devices. Here, we present a memory device fabricated with graphite membrane, which has a simple two terminal planar structure and high ON/OFF ratio over $10^{2}$ . We use the memory device to establish logic gates, and stateful logic operations were successfully carried out. This letter paves the way for carbon electronics to be used in new computation technology.

This letter investigates the switching behavior of TaN/Al2O3:Ag:ZnO/ITO memristors fabricated on flexible substrates, for flexible nonvolatile memory and neuromorphic computing applications. The embedded Ag nanoparticles provide for improved device yield and reduced variability in resistance, from more than 160% to 30%. They also provide for reduced variability in set and reset voltages, from 35% to 18% and 40% to 11%, respectively. A synaptic behavior of this flexible device is demonstrated, making it a potential candidate for neuromorphic circuit applications. Furthermore, its low-power requirements make it more competitive for emulating biological systems.

A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS2 channel and Al2O3 gate dielectric. To avoid a possible noise signal contamination from the top MoS2 surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS2 are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS2/Al2O3 interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from $4\times 10^{10}$ cm $^{\mathrm {-2}}$ in the weak over-drive region to $5\times 10^{11}$ cm $^{\mathrm {-2}}$ in the strong over-drive region.

Amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor nonvolatile memory devices with an IGZO charge storage layer were evaluated for the first time for multi-level cell memory applications. The pristine device was defined as the original state (OS), which can be switched to the programmed state (PS) after a positive gate voltage pulse (for example, 12 V for 10 ms), and to the erased state (ES) after a negative gate voltage pulse (for example, −15 V for 10 ms). The writing mechanism was attributed to Fowler–Nordheim tunneling of electrons from the channel to the charge storage layer under a positive gate bias and inverse tunneling under a negative gate bias. The devices demonstrated superior electrical programmable and erasable characteristics. A memory window of 2.4 V between OS and PS was maintained after 100 programming/erasing cycles, and a memory window of 2.66 V between OS and ES as well. The memory windows relative to OS are equal to 1.91 and 1.30 V for PS and ES, respectively, for a retention time of $10^{5}$ s.

The impacts of postdeposition annealing in O2 on the electrical performance of atomic-layer-deposited ZnO thin-film transistors (TFTs) have been investigated. The TFTs are fabricated on transparent quartz substrates with Al2O3 dielectrics, ZnO active layers, and Cr/Au electrodes. The best field-effect mobility of 21.3 $\mathrm{cm}^{2}$ /Vs and a large ON/OFF current ratio of $10^{7}$ are obtained under 400 °C annealing treatment in O2. Furthermore, analysis indicates that reduction of OH bonds in both ZnO and Al2O3 layers is the key issue to achieve the excellent properties.

Metal-insulator-metal (MIM) capacitors with full atomic-layer-deposition Al 2 O 3 /ZrO 2 /SiO 2 /ZrO 2 /Al 2 O 3 stacks were explored for the first time. As the incorporated SiO 2 film thickness increased from 0 to 3 nm, the quadratic and linear voltage coefficients of capacitance (α and β) of the MIM capacitors reduced significantly from positive values to negative ones. For the stack with 3-nm SiO 2 film, a capacitance density of 7.40 fF/μm 2 , α of -121 ppm/V 2 , and β of -116 ppm/V were achieved, together with very low leakage current densities of 3.08 × 10 -8 A/cm 2 at 5 V at room temperature (RT) and 5.89 × 10 -8 A/cm 2 at 3.3 V at 125 °C, high breakdown field of 6.05 MV/cm, and high operating voltage of 6.3 V for a 10-year lifetime at RT. Thus, this type of stacks is a very promising candidate for next generation radio frequency and analog/mixed-signal integrated circuits.

Semiconducting amorphous indium-gallium-zinc oxide (a-IGZO) films are integrated with an Al2O3/Pt-nanocrystals/ Al2O3 gate-stack to form UV-erasable thin-film transistor (TFT) memory. The threshold voltage (Vth), subthreshold swing, ION/IOFF ratio, and effective electron mobility of the fabricated devices are 2.1 V, 0.39 V/decade, ~106, and 8.4 cm2/V·s, respectively. A positive Vth shift of 2.25 V is achieved after 1-ms programming at 10 V, whereas a negative Vth shift as large as 3.48 V is attained after 5-s UV erasing. In addition, a 10-year memory window of 2.56 V is extrapolated at room temperature. This high-performance a-IGZO TFT memory is suitable for optical touch-panel applications.

Variations in SET and RESET voltages during resistive switching cause problems for transition-metal-oxide-based resistive memory applications. The random circuit breaker network model has illustrated that the random formation and rupture of conducting filaments result in this instability. A solution consisting of a carefully designed electric field redistribution is proposed to minimize these variations. This switching behavior occurs in an ultrathin Al2O3 film very near to the anode rather than occurring in a random distribution over a large region. The SET voltage distribution is narrowed by a factor of seven, and consequently, the RESET voltage distribution is confined near a fixed value.

Resistive switching behaviors of Al2O3-based memory devices with and without ruthenium nanocrystals (RuNCs) fabricated by atomic layer deposition are investigated for nonvolatile-memory applications. Large resistance ratios (>; 105) of high- to low-resistance states were observed with nanocrystals contribution. Moreover, improvements of stability device yield and retention performance were also achieved by embedding RuNCs. Therefore, the Al2O3-based resistive memory device composed of embedded nanocrystals is a possible solution for future integrated standalone storage class memory processes.

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.

It is demonstrated that the voltage coefficients of capacitance (VCC) in high-/spl kappa/ metal-insulator-metal (MIM) capacitors can be actively engineered and voltage linearity can be significantly improved maintaining high capacitance density, by using a stacked insulator structure of high-/spl kappa/ and SiO/sub 2/ dielectrics. A MIM capacitor with capacitance density of 6 fF/spl mu/m/sup 2/ and quadratic VCC of only 14 ppm/V/sup 2/ has been demonstrated together with excellent frequency and temperature dependence (temperature coefficients of capacitance of 54 ppm /spl deg/C) as well as low leakage current of less than 10 nA/cm/sup 2/ up to 4 V at 125 /spl deg/C.

Amorphous In–Ga–Zn–O (a-IGZO) thin-film transistor with an atomic-layer-deposited (ALD) SiO2 gate insulator was fabricated under a maximum processing temperature of 250 °C and compared with the counterpart with a plasma-enhanced chemical vapor deposited (PECVD) SiO2 gate insulator. It was demonstrated that the ALD SiO2 insulator could generate much better device performance than the PECVD one. This is attributed to a lower density of interfacial traps, weaker surface roughness scattering, and enhanced passivation of oxygen vacancies in the a-IGZO channel atop the ALD SiO2 film with more OH groups. Without the need of post-annealing, the ALD SiO2 device exhibited very good stability under a negative gate bias stress (−15 V), while maintaining superior performance such as quite high field effect mobility of 63.6 cm $^{2}~\text{V}^{-1}\text{s}^{-1}$ , a low threshold voltage of −0.10 V, a small subthreshold swing of 0.14 V/decade, and a large ON/OFF current ratio of $\sim 10^{8}$ .

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.

The excellent resistive switching characteristics of atomic-layer-deposited HfLaO-based devices are investigated for nonvolatile memory applications. With the help of nonlattice oxygen ions which is designed to incorporate into the film by decomposition of H2O2 during process, highly uniform and reproducible resistance switching cycles could be observed with the resistive ratio as high as 106 for more than 10 000 cycles. In addition, the fast operation speed (10 ns) has been demonstrated. Conduction of the off state is dominated by the space-charge-limited hopping, while the ohmic behavior dictates the on state, which suggests a filamentary conduction mechanism. Moreover, the estimated readout characteristics under different read voltages from 0.3 to 1 V were sufficiently stable to fulfill the requirement for memory application. Considering the excellent memory switching behavior, a resistance switch device composed of a promising high-k HfLaO dielectric film is a possible candidate to be integrated into future memory processes.