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Your search keyword '"Kosuge, Atsutake"' showing total 6 results
Start Over Author "Kosuge, Atsutake" Journal ieee journal of solid-state circuits
6 results on '"Kosuge, Atsutake"'

3. A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Author

Shiba, Kota, Okada, Mitsuji, Kosuge, Atsutake, Hamada, Mototsugu, and Kuroda, Tadahiro

Abstract

A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling interchip wireless communication interface for a 3D- stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET process. A new physical placement method that allows coils to be placed over off-the-shelf SRAM macros with small magnetic field attenuation, together with the use of synchronous communication using Manchester encoding and a clocked comparator to enable the detection of small-swing signals, achieves a 26% reduction in SRAM die area compared to through-silicon via (TSV)-based stacking. Interchip communication at 0.7 pJ/bit, 8.5 Gb/s/link was confirmed using test chips. A 4-hi 3D- stacked SRAM module using the proposed interface achieves a 1.2-TB/s/mm2 area efficiency, representing a two orders-of-magnitude improvement over the state-of-the-art 3D- stacked SRAM.

Published
2023
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6. An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories.

Author

Kosuge, Atsutake, Hashiba, Junki, Kawajiri, Toru, Hasegawa, So, Shidei, Tsunaaki, Ishikuro, Hiroki, Kuroda, Tadahiro, and Takeuchi, Ken

Subjects
HARD disks, SOLID state electronics, FLASH memory, ERROR-correcting codes, WIRELESS communications, DATA transmission systems
Abstract

A highly reliable wireless solid-state drive (SSD) system for future applications of large volume storage is presented. The wireless interface in the system consists of an inductively coupled power link with fast transmission power control and high-speed data links using transmission line couplers (TLCs). The wireless power link can deliver 1 W from the host to the SSD. The full duplex wireless data interface achieves raw data rate of 1.6 Gb/s. The reliability of the wireless interface is studied though simulation analysis and experiments. The error correction block for the NAND flash memory system can also correct errors in the wireless data links, allowing the requirements for the PHY layer to be relaxed. The error correction code is discussed, including optimization by analyzing the error bits on the wireless data links. The experimental results confirmed strong tolerance to the interference from the power link on the wireless data link, and the water proof property of both the data and power links. [ABSTRACT FROM PUBLISHER]

Published
2016
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