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A highly reliable wireless solid-state drive (SSD) system for future applications of large volume storage is presented. The wireless interface in the system consists of an inductively coupled power link with fast transmission power control and high-speed data links using transmission line couplers (TLCs). The wireless power link can deliver 1 W from the host to the SSD. The full duplex wireless data interface achieves raw data rate of 1.6 Gb/s. The reliability of the wireless interface is studied though simulation analysis and experiments. The error correction block for the NAND flash memory system can also correct errors in the wireless data links, allowing the requirements for the PHY layer to be relaxed. The error correction code is discussed, including optimization by analyzing the error bits on the wireless data links. The experimental results confirmed strong tolerance to the interference from the power link on the wireless data link, and the water proof property of both the data and power links. [ABSTRACT FROM PUBLISHER]

A 0.79-mm² 29-mW real-time face detection core is fabricated in a 0.13-μm CMOS technology. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The core can detect eight faces in each frame of moving pictures at 30 frames/second. Face detection accuracy is 92%. [ABSTRACT FROM AUTHOR]

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-µm CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of ±2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10-3. For ranging applications, the transmitter can reduce the power to 0.7 µW for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 µV/m, and thus the UWB system can be operated even under the current Japan radio regulations. [ABSTRACT FROM AUTHOR]

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2 W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-μm pitch in 0.25-μm CMOS technology. By thinning chip thickness to 10 μm, the interface communicates at distance of 15 μm at minimum and 43 μm at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk. [ABSTRACT FROM AUTHOR]

A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10-12 by laboratory measurements. [ABSTRACT FROM AUTHOR]

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-µm CMOS technology. The receiver active area is 0.8 mm² and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10-12. The areas and power consumptions are 47 µm × 85 µm and 13.2 mW for the equalizer, and 145 µm × 80 pm and 10 mW for the ISI monitor. [ABSTRACT FROM AUTHOR]

A wireless bus for stacked chips was development by utilizing inductive coupling among then inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive are designed for inductive nonreturn-to-zero where no signal is transmitted when data remains the same. At test chip was fabricated in 0.35-μm CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 42 and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 μm in 90-nm device generation,power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm2. [ABSTRACT FROM AUTHOR]

The article features Tadahiro Kuroda and Stephen V. Kosonocky and the selection of the best papers from the 2005 Symposium on VLSI Circuits, which was held at the Rihga Royal Hotel, Kyoto, Japan on June 16-18, 2005. The Symposium marked its 19th annual meeting, establishing itself as a major international forum presenting developments in VLSI circuit design. Tadahiro Kuroda received the Ph.D. degree in electrical engineering from the University of Tokyo and worked for Toshiba Corporation while Stephen V. Kosonocky received the Ph.D. degree from Rutgers University in New Jersey and worked for Siemens, Samsung and IBM.

Introduces the articles in the April 2005 issue of the periodical "IEEE Journal of Solid-State Circuits". Papers from the 2004 Symposium on VLSI Circuits; Number of submissions accepted by the Symposium.