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Availability of a reliable ON-chip oscillator can secure a system-on-chip (SoC) against physical clock attacks by enabling applications such as boot-up using ON-chip oscillator and hardware clock monitors. This article proposes a frequency-error feedback (FEF) loop-based relaxation oscillator for such applications. It suppresses the low-frequency noise and improves the time interval error (TIE) without degrading the period jitter. It also stabilizes the oscillator against supply and temperature variations. A 77-MHz oscillator prototype is fabricated in a commercial 5-nm FinFET process. Operating from 0.9-V digital and 1.2-V analog supplies, the prototype consumes a total of 0.84 mW and occupies an area of 0.0152 mm 2. It achieves a TIE of 3 ns over 10 K cycles which is $3\times $ better than an oscillator without an FEF loop. Chip samples are picked from four wafer split lots. The worst case frequency variation measured from 16 samples is $\pm 0.25\%$ across an analog supply change of 1.1–1.35 V, while a variation of $\pm 0.3\%$ is measured over −40 to $125 ^\circ \text{C}$ temperature from eight samples. [ABSTRACT FROM AUTHOR]

This article presents a bipolar junction transistor (BJT)-based CMOS temperature-to-frequency converter (TFC). A relaxation oscillator (ROSC) consisting of an integrating capacitor, a current source, and a comparator converts the ratio of the complementary-to-absolute-temperature (CTAT) voltage to the proportional-to-absolute-temperature (PTAT) voltage created by the BJT core to frequency. To improve the temperature accuracy, we incorporate a capacitor flipping technique to remove an offset of the comparator and a settling time error when resetting the integrating capacitor. Moreover, bootstrapped NMOS switches with the triple well structure are implemented to suppress leakage current and prevent from forming parasitic BJTs when the negative CTAT is applied to them by the proposed flipping technique. The prototype fabricated in a 0.11- $\mu \text{m}$ CMOS process consumes 3.1- $\mu \text{W}$ power and occupies a 0.025-mm2 active area. Measurements of 18 samples with the digital trimming show an inaccuracy of $\pm 1~^{\circ }\text{C}$ ($3\sigma$) from $- 40\,\,^{\circ }\text{C}$ to $140~^{\circ }\text{C}$. The area- and energy-efficient TFC is applicable to monitor the temperature inside integrated chips. [ABSTRACT FROM AUTHOR]

This article describes a 2.1-MHz relaxation oscillator (RxO) for energy-harvesting Internet-of-Things (IoT) sensor nodes. The RxO features an asymmetric swing-boosted RC network and a dual-path comparator to surmount the challenges of sub-0.5-V operation while achieving temperature resilience. The former enables alternating the common-mode voltages at the output of the RC network to facilitate the sub-0.5-V operation, while the latter is outfitted with a delay generator for tracking the temperature-sensitive delay of the comparator. Prototyped in 28-nm CMOS, the RxO occupies a tiny footprint of 5,200 μm2. The power consumption is 1.4 μW at 0.35 V. The measured temperature stability is 158 ppm/°C (average of seven chips) over −20 °C–120 °C. It scores the best energy efficiency (667 fJ/cycle) among the reported MHz-range RxOs and has a figure-of-merit (181 dB) that compares favorably with the state-of-the-art. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated stand-alone narrowband Internet-of-Things (NB-IoT) and global navigation satellite system (GNSS) system-on-chip (SoC). It aims for an all-in-one system to integrate all necessary blocks such as an RF transceiver, a power management system (PMIP), and a clock management system and to save a bills-of-material (BOM) cost. An RF transceiver is integrated to support multi-band cellular IoT and GNSS with a CMOS RF power amplifier transmitting 23-dBm output power. A PMIP, including bucks, a boost, and low-dropout regulators (LDOs), is integrated to support coin cell or AAA battery and to support a wide input supply voltage range from 2.5 to 5 V. In addition, clock management system is embedded with a digitally controlled crystal oscillator (DCXO), a relaxation oscillator (RCO), and temperature sensor units (TSUs). It is fabricated in a standard 28-nm CMOS process and its size is 24.6 mm2. The power consumption of always-on-block is 15 $\mu \text{W}$ , and the sleep current consumption is less than 10 $\mu \text{A}$ at 3.8 V. [ABSTRACT FROM AUTHOR]

This article presents an ultra-low-noise differential relaxation oscillator that achieves a phase noise figure of merits (FoMs) of 157.7 and 162.1 dBc/Hz, respectively, at 1- and 100-kHz frequency offsets. The oscillator is inherently robust against 1/f noise, while swing-boosting minimizes the phase noise arising out of thermal noise. Furthermore, an inverter-based differential comparator maximizes power efficiency, enabling FoMs close to the fundamental limits. Operating at 10.5 MHz and consuming 219.8 μW from a 1.4-V supply, the oscillator achieves a period jitter of 9.86 psrms, equivalent to a relative jitter of 0.01%. The oscillator occupies an active area of 0.015 mm2 in a 0.18-μm standard CMOS process. [ABSTRACT FROM AUTHOR]

Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz—a 4 $\times $ improvement over state-of-the-art for comparable stability. [ABSTRACT FROM AUTHOR]

This paper presents a theoretical study and design of two techniques used to reduce start-up time ($T_{S}$) and energy ($E_{S}$) of Pierce crystal oscillator (XO). An analytical study of precise injection on a crystal resonator is introduced, and based on this paper, a relaxation oscillator with a dithered frequency is designed. Next, a study of negative resistance of XO’s active circuitry and a method to boost its value beyond the limit set by a crystal static capacitor are presented. A gyrator-C active inductor with high linearity is developed to accelerate the start-up process by boosting the negative resistance. A prototype integrating these techniques is fabricated in a 180-nm CMOS process and shows a significant improvement compared with the prior art. Specifically, $T_{S}$ and $E_{S}$ are reduced by 102.7 $\times $ and 2.9 $\times $ , compared with the XO start-up with no assisting circuitry, to 18 $\mu \text{s}$ and 114.5 nJ for a 48-MHz XO across a temperature range of −40 °C to 90 °C. The measured steady-state power and the phase noise of the XO are 180 $\mu \text{W}$ and −135 dBc/Hz at 1-kHz offset. [ABSTRACT FROM AUTHOR]

A number of specialized topics within the theory of injection locking and pulling are addressed. The material builds on our impulse sensitivity function (ISF)-based, time-synchronous model of electrical oscillators under the influence of a periodic injection. First, we show how the accuracy of this model for $LC$ oscillators under large injection is greatly enhanced by accounting for the injection’s effect on the oscillation amplitude. In doing so, we capture the asymmetry of the lock range as well as the distinct behaviors exhibited by different $LC$ oscillator topologies. Existing $LC$ oscillator injection locking and pulling theories in the literature are subsumed as special cases. Next, a transient analysis of the dynamics of injection pulling is carried out, both within and outside of the lock range. Finally, we show how our existing framework naturally accommodates locking onto superharmonic and subharmonic injections, leading to several design considerations for injection-locked frequency dividers (ILFDs) and the implementation of a low-power dual-modulus prescaler from an injection-locked ring oscillator. Our theoretical conclusions are supported by simulations and experimental data from a variety of $LC$ , ring, and relaxation oscillators. [ABSTRACT FROM AUTHOR]

Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 $\mu \text{W}$ /MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator’s delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50–300 MHz output frequencies from a reference clock in the range of 0.5–5 MHz. The DPLL occupies an active area of 125 $\mu \text{m}\times125\mu \text{m}$ and achieves ±0.33% period jitter while consuming 63.5 $\mu \text{W}$ at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 $\mu \text{W}$ /MHz at 0.8-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0–40°C. The TC increases to 4.3 ppm/°C over the range from −15 °C to 55 °C. The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is $69~\mu \text{W}$ with a 1-V supply, and the leakage power consumption is 110 nW, while power gated. The ROSC achieves a fast startup time of $8~\mu \text{s}$ by employing a voltage buffer to quickly stabilize the voltage reference. [ABSTRACT FROM AUTHOR]

This paper presents a readout IC that uses an asynchronous capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. A power-efficient tracking algorithm ensures that the CDC consumes negligible power consumption in the absence of touch events. To facilitate its use in wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low-power relaxation oscillator. At a 38-Hz scan rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date. [ABSTRACT FROM AUTHOR]

In this paper, a pW-power relaxation oscillator for sensor node applications is presented. The proposed oscillator operates over a wide supply voltage range from nominal down to deep sub-threshold and requires only a sub-pF capacitor for Hz-range output frequency. A true pW-power operation is enabled thanks to the adoption of an architecture leveraging transistor operation in super-cutoff, the elimination of voltage regulation, and current reference. Indeed, the oscillator can be powered directly from highly variable voltage sources (e.g., harvesters and batteries over their whole charge/discharge cycle). This is achieved thanks to the wide supply voltage range, the low voltage sensitivity of the output frequency and the current drawn from the supply. A test chip of the proposed oscillator in 180 nm exhibits a nominal frequency of approximately 4 Hz, a supply voltage range from 1.8 V down to 0.3 V with 10%/V supply sensitivity, 8–18-pA current absorption, and 4%/°C thermal drift from -20 °C to 40 °C at an area of $1600~\mu \mathrm {m}^{2}$. To the best of the authors’ knowledge, the proposed oscillator is the only one able to operate from sub-threshold to nominal voltage. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated, 8.2-MHz relaxation oscillator with a self-threshold-tracking loop and swing-boosting technique for improving its long-term frequency stability and noise performance. The proposed latch-based relaxation oscillator increases the transition speed to reduce the static power consumption. To decrease the process–voltage–temperature dependence, we propose a self-threshold-tracking loop to ensure that the transition point of the inverter-based comparator is set to a fixed ratio of the supply voltage. In addition, the comparator delay can be compensated by the tracking loop, relaxing the requirements of comparator power consumption. The design is implemented in a 0.18- $\mu \text{m}$ CMOS process. The design achieves a period jitter of 7.66 psrms, the phase noise of −109 dBc/Hz at an offset frequency of 100 kHz, and an Allan deviation noise floor of 1.56 ppm. The resultant figure of merit is 160.8 dBc/Hz, while only consuming 46.3 $\mu \text{W}$. The power efficiency of the design is 5.6 kHz/nW. As for the supply sensitivity, the design achieves 0.9 %/0.1 V, which is 10 $\times $ lower than the design with no compensation loop. The measured temperature coefficient of the proposed oscillators is 123 ppm/°C from −20 °C to 100 °C without any trimming process. [ABSTRACT FROM AUTHOR]

An ultra low-energy oscillator circuit is presented for use in picowatt level systems. The core oscillator uses an 18 transistor 3 stage architecture designed to minimize short circuit current. In addition, a transistor threshold is used to set the trip point as opposed to a voltage reference and comparator scheme, leading to overall energy savings. While operating across a wide range of low frequencies from 18 to 1000 Hz, the oscillator core consumes 110 fJ/cycle at 0.6 V. The circuit is demonstrated alongside an integrated current source to set the reference frequency. The combined system consumes a total power of 4.2 pW at 18 Hz, resulting in 230 fJ/cycle at 0.6 V. [ABSTRACT FROM PUBLISHER]

An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging feedback (VAF) concept is proposed to overcome conventional relaxation oscillator problems such as sensitivity to comparator delay, aging, and flicker noise of current sources. A test-chip with typical frequency of 14.0 MHz was fabricated in a 0.18 µm standard CMOS process and measured frequency variations of 0.16% for supply changes from 1.7 to 1.9 V and ± 0.19% for temperature changes from -40 to 125°C. The prototype draws µ25 A from a 1.8 V supply, occupies 0.04 mm mm² and achieves 7 reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF. [ABSTRACT FROM AUTHOR]

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22°C to 85°C. Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm² and draws 34 μA from a 1.2 V supply at room temperature. [ABSTRACT FROM AUTHOR]

We present a novel physical random number generator (RNG) that uses a metal-oxide semiconductor (MOS) capacitor after soft breakdown (SBD) as a random source. It is known that the electrical properties of MOS capacitors after SBD show large fluctuation. When the resistor in an astable multivibrator is replaced with an MOS capacitor after SBD, the multivibrator converts the noise signal into a rectangular wave whose period fluctuates randomly. A 1-bit counter and a flip-flop are used to generate random numbers from the fluctuating rectangular wave. Some high-level tests indicate that the generated random numbers have excellent quality for cryptographic applications. Even though our circuit is small and can be constructed using about 20 complementary-MOS logic gates and several passive devices, high-quality random numbers such as those generated by large physical RNGs can be obtained. [ABSTRACT FROM AUTHOR]