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In this work, for the first time, a machine learning behavioral modeling methodology based on gate recurrent unit (GRU) is developed and used to model and then analyze the kink effects (KEs) in the output reflection coefficient $(S_{22})$ and the short-circuit current gain $(h_{21})$ of an advanced microwave transistor. The device under test (DUT) is a 0.25- $\mu \text{m}$ gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC) substrate, which has a large gate periphery of 1.5 mm. The scattering (S-) parameters of the DUT are measured at a frequency up to 65 GHz and at an ambient temperature up to 200°C. The proposed model can accurately reproduce the KEs in $S_{22}$ and in $h_{21}$ , enabling an effective analysis of their dependence on the operating conditions, bias point and ambient temperature. It is worth noticing that the proposed transistor model shows also good performance in both interpolation and extrapolation test.

The origin of a greater decrease in kink drain voltage $V_{kink}$ in floating body PD-SOI MOSFETs with gate lengths shorter than $0.35 ~\mu m$ is newly revealed. The $V_{kink}$ formula as a function of the internal body voltage and $I_{DS}$ is derived by combining the modified impact ionization multiplication factor with the body-source junction I-V equation. The parameters in this formula are extracted from the measured data of $I_{B}$ vs. $V_{BS}$ and ${- I}_{B}/I_{DS}$ vs. $V_{DS}$ in the body contacted devices. By calculating the formula using the extracted parameters, it is newly found that a decrease of the drain-source saturation voltage at a shorter channel is a primary cause for the short-channel effect on $V_{kink}$ reduction.

In this paper, kink effect observed in the output characteristics of the AlInN/GaN-on-Si high electron mobility transistor (HEMT) after subjecting the Si-substrate to positive/negative bias stress has been studied. The charge distribution in the different buffer layers of the wafer in the presence of different substrate-bias stress has been discussed in detail. It is concluded that the induced kink is due to the trapping/de-trapping of charge carriers through acceptor-like deep levels present in the GaN buffer layer. TCAD simulations have been performed to understand the electric-field distribution within the device layers, which is strongly related to the observed kink phenomenon. Two types of traps, acceptor-like (Ea1 = 0.52 eV) and donor-like (Ea2 = 0.44 eV), were extracted from temperature-dependent drain current transient analysis using back-gating experiment. It is concluded that a carbon-induced deep acceptor-like trap is responsible for the observed kink effect.

Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

Four-terminal poly-Si thin-film transistors (TFTs), with a counter-doped body terminal connected to the floating channel, can suppress both dc and dynamic hot-carrier (HC) degradation of TFTs. With 3-D TCAD simulation, we clarify the underlying mechanisms of the suppression effect and analyze its dependence on the position and width of the body terminal. Under dc HC condition, a wider body terminal or that closer to the drain collects more holes generated from impact ionization in the drain depletion region and suppresses the parasitic bipolar junction transistor effect, subsequently reduces the kink current more effectively. Under dynamic HC condition, the body terminal injects holes at the end of the falling time of the gate pulse, partially removes the non-equilibrium state, significantly relieves the transient maximum electric field in the drain depletion region, thus suppresses the dynamic HC degradation. A wider body terminal can inject more holes and the holes injected by that closer to the drain diffuse to drain depletion region first, thus suppress the dynamic HC degradation better.