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Although published research in COSL has stagnated, it remains a useful logic family for interfacing the much faster RSFQ family to hot-logic circuits. COSL has always been plagued by the absence of latches, and previous attempts at implementing such latches were clumsy. A new COSL Set-Reset flip-flop is discussed here, and results shown. This asynchronous input latch, which can also be configured as a T flip-flop, can function on a single-phase clock. It was also adapted to convert SFQ output pulses from RSFQ logic circuits to voltage state levels that can be viewed on standard laboratory oscilloscopes. Due to the asynchronous nature of the inputs, the RSFQ-COSL converter is also more reliable than earlier DRO-to-COSL elements.

A new RSFQ latch, the DC-Resettable Latch (DCRL), is introduced. The DCRL functions like a standard nondestructive readout register (NDRO), except that it requires a dc current or current pulse to reset. This allows the DCRL to be used as a memory element in large memory blocks, where the entire block can be erased with a current pulse from a single threaded current line instead of unwieldy pulse distribution circuitry. The reset current can be applied by off-chip control logic, or on-chip bipolar current elements such as HUFFLEs. However, the DCRL is most useful as the base building block of complex reprogrammable RSFQ circuitry.

One of the remaining challenges in the application of superconducting electronics is the interfacing between superconducting and semiconducting environments. The voltage and speed mismatch between RSFQ pulses and semiconducting read-out electronics makes it necessary to amplify as well as stretch the RSFQ pulses. Moreover, circuits based on HTS (High Temperature Superconductor) technology are very attractive since they can operate under considerably relaxed cooling effort, which is one of the main problems with LTS (Low Temperature Superconductor) circuits. Within the European project SuperADC, a HTS second order sigma delta modulator and a pulse stretcher, used as an interface between the modulator and the first semi-conducting amplifier stage, have been designed at Twente University and will be presented here.

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.

All complex devices in rapid single flux quantum (RSFQ) technique work at much lower clock rates than possible for simple cells. New data driven self timed or asynchronous concepts can reduce this gap, but even in this case still a discrepancy between simulation and experiment is shown. It has been pointed out in previous studies, that the influence of thermal fluctuations in RSFQ circuits is divided into static and dynamic switching bit errors as well as timing jitter induced failures. The bit error rate depends exponentially on the temperature and is not the main issue in the low temperature technique. Our last results show for the first time, that the variance of the switching time is much slower decreased by reducing the temperature and is still important at 4.2 K. We describe a general method for calculating the switching time distribution for RSFQ cells. Furthermore, we present detailed results for a timing analysis of a dc/SFQ-converter. The delay between output signal and the input current ramp shows a variation over 1 ps which is more than 10% of the switching time itself. This new understanding of the background of timing jitter enables a goal-oriented improvement in the design process of RSFQ circuits.

The voltage multiplier (VM) is a principal component in high-precision digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) circuits. Experimental confirmation of correct operation of the VM is important to guarantee the accuracy of the D/A converter. In this study, a circuit for direct comparison of the output voltages of VMs was designed and demonstrated. An on-chip SQUID sensor was utilized to detect the VM errors. Bit error rates of a single-stage VM were successfully measured down to 10/sup -12/ in the constant-voltage regions. A method of detecting errors during transients was also proposed and carried out.

Compact mm/submm integrated spectrometers are required for radio-astronomical research, remote monitoring of the Earth atmosphere and environmental monitoring for hazardous materials of chemical and biological origin. Assembled on a multi-chip module the all superconducting integrated spectrometer offers integration of thin film analog components such as a mixer, superconducting local oscillator and an intermediate frequency SQUID amplifier together with superconducting digital circuitry. A Rapid Single Flux Quantum (RSFQ) 128-bit autocorrelator formed by 16-bit autocorrelator and a 112-bit programmable shift register that adjusts the data delay in increments of 16, is used for digitizing of the down converted signals and real-time digital processing. Experimental results showing both operation of components and the way to their successful integration are presented.

At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.

Complex RSFQ circuits are typically dc-biased with one or more current bias trees, with current returning through a superconducting ground plane. As the bias currents become larger in more complex circuits, it is increasingly critical to pay attention to the distribution of these return currents, and the effects of the resulting magnetic fields on the performance of the RSFQ circuits. We have modeled the current and field distributions, and found that magnetic field and flux are indeed significant. This has been confirmed by direct measurement using a distribution of SQUIDs. Furthermore, we have measured the performance of several RSFQ circuits, and have found that currents in the ground plane can significantly affect performance margins. Approaches to circuit and system designs that can reduce these problems are discussed.

The Rapid Single Flux Quantum (RSFQ) technique is regarded as one of the most promising electronics due to its extremely high operating speed and low power consumption. Middle-scale RSFQ applications operating at multigigahertz frequency have recently been reported on. At such high operating frequencies, the on-chip interconnects start to play a limiting role for the performance of the densely packaged digital circuits. Our previous studies have theoretically investigated the parasitic coupling effects between superconductive microstrip transmission lines and conclusions have been drawn about the critical coupling levels of several typical microstrip geometries. Here, basic RSFQ structures are investigated experimentally, which contain a Josephson transmission line stage with large inductance and can either trap or pass SFQ pulses. These structures are incorporated in critical microstrip layouts, thus being subjected to parasitic coupling. The bias levels are monitored at which the structures start to pass the SFQ pulses with and without coupling influences. Thus, the conclusions of our previous theoretical investigations are verified experimentally.

Fast on-chip control of superconducting qubits has engaged complex and power consuming RSFQ circuits that currently pose more of an experimental burden than an asset. Measurements of quantum coherent oscillations of qubits require dilution refrigerator temperatures. The motivation of this design is to minimize the necessary bias leads and power dissipation for an SFQ based control circuit. Elimination of redundant circuit elements by innovative use of fundamental elements allows small-scale control circuitry.

Manufacturing tolerances influence circuit parameters, and inductance is no exception. A computer application was developed to fully automate inductance calculation as part of a layout extraction suite. InductEx takes a GDSII layout file as input, finds the inductance ports, extracts structures, applies mask-to-wafer offsets and random process tolerances to the circuit structures, builds deck files that can be processed with FastHenry, and manages FastHenry-all autonomously. Results are presented for the simulated variation in inductance-both self and mutual, over hundreds of runs-in several common RSFQ structures in the Hypres 1 kA/cm/sup 2/ process (with the latest tolerance values built in), even with the presence of moats.

Two effects of the bias supply line on the performance of RSFQ circuits have been studied: inductive coupling between the bias supply line and circuit inductances; effect of the mirrored current in the ground plane. The following results of the study are presented: 3D calculations and experimental measurements of inductive coupling between parallel and perpendicular microstrips in presence of one and two ground planes; calculated margins dependence on the external magnetic field in RSFQ cell. Bias current density extraction method has been developed and implemented in RSFQ circuit design flow.

As part of the effort to develop a superconductive microprocessor, we constructed a rapid single flux quantum (RSFQ) 4-bit arithmetic and logic unit (ALU) in a pipelined structure. To speed up the circuit, we used a forward clocking scheme. The 4-bit ALU consisted of ten RSFQ Half Adders, four 2 /spl times/ 2 switches, and several D flip-flops. By commutating output ports of the half adder, we were able to produce AND, OR, XOR, and ADD functions. The 4-bit ALU was fabricated using the Korea Photonics Technology Institute's ten-level 1.0 kA/cm/sup 2/ Nb process. The size of the ALU was 3.0 mm /spl times/ 1.5 mm, fitting in a 5 mm /spl times/ 5 mm chip. The fabricated 1-bit ALU block was successfully tested at up to a 40 GHz clock frequency. The complete 4-bit ALU operated correctly at up to a 5 GHz clock frequency.

We describe recent demonstration of a superconductor oscillator/counter A/D Converter up through 12 GS/s with 3 effective bits of signal-to-noise ratio at that sample rate, along with analysis of its performance. Measurements are described for an A/D converter implemented in Northrop Grumman Space Technology's 4 kA/cm/sup 2/ J110D Niobium process. This A/D Converter incorporates a new technique for defining the aperture using inter-Josephson transmission line SFQ repulsion. This technique is described here.

Currently, when a new fabrication process becomes available, all logic cells have to be re-designed, re-optimized and laid out from scratch. This is a manual and time intensive process, which hampers the migration of RSFQ circuits to better fabrication processes. The paper investigates the parameters that are required to specify logic gates that are technology and fabrication process independent. Ways of automating the optimization of the logic gates for implementation in new technologies, and automating the layout of logic cells for new design rules or new fabrication processes, are described. Cells can then be characterized for implementation in both LTS and HTS processes. Steps in the development of new logic gates and automation processes are shown.

This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.

The speed of Josephson circuits such as those required for rapid single flux quantum logic is limited by the Josephson plasma frequency, /spl omega//sub p/, which (with few exceptions) increases monotonically with increasing critical current density, J/sub c/. Here we describe a new technique for directly measuring /spl omega//sub p/, using the current-voltage characteristics of a simple structure based on externally-shunted, series-connected tunnel junctions. We present both experimental and theoretical demonstrations of the technique and describe its application to the determination of the junction capacitance, a property poorly characterized for high-J/sub c/ junctions.

A pulse-number multiplier (PNM) is a principal subsystem of our rapid single flux quantum digital-to-analog converter for metrology applications. The PNM circuit generates a high-speed pulse train from an input of a precise low-frequency clock signal. We designed, fabricated, and successfully tested a PNM test circuit. The PNM test circuit was implemented by using our standard cell library on 1.6 kA/cm/sup 2/ Nb trilayer technology. Fully functional operation was confirmed by low-speed testing. Experimental bias margins were wider than /spl plusmn/20%, and these results agreed with a simulation. We also tested the circuit by average-voltage measurements for estimating the frequencies of output pulse trains. Results of average-voltage measurements implied that the output frequency of the PNM circuit was tunable from 5 GHz to 17 GHz. The bit error rate (BER) of the PNM circuit was measured, and extrapolation of the error-function fits suggested a sufficiently small BER at the optimum bias point.

For high sensitive measurements of small magnetic fields a Digital SQUID is superior to conventional analog SQUIDs in terms of dynamic properties, but recent realizations as single-flux-quantum (SFQ) circuit suffers from high complexity. A new kind of Digital SQUID as a full digital sensor device with the advantage of a small number of Josephson junctions and a large slew rate was developed. The circuit consists of basic SFQ cells and an internal digital feedback loop. The operation with a bidirectional clock signal ensures a decreased effort on superconducting electronics. The SFQ/dc converter and an additional voltage driver provides a processable digital output signal for hybrid systems including semiconductor electronics. The sensor circuit was simulated, optimized and fabricated in niobium technology. From investigation of dynamic properties of the circuit we expect a flux slew rate in the gigahertz range.

Asynchronous timing is very important in the design of large-scale ultra-high speed superconducting digital electronic (SDE) circuits. This paper presents an optimized asynchronous self-timing scheme that will simplify and speed up the design of large digital circuits. Rapid Single Flux Quantum Asynchronous Timing (RSFQ-AT) is compared to other timing schemes by implementing, testing and evaluating a variety of circuits. Further it is shown how the design methodology introduced with this asynchronous self-timing scheme can simplify the design of automated CAD tools for RSFQ-AT.

The HYPRES 3.0 /spl mu/m niobium (Nb) process has proven to be capable of realizing complex low temperature superconductor (LTS) rapid single flux quantum (RSFQ) circuits. In such a mature fabrication process, the importance of the detection of random defects is crucial as they contribute to the majority of the defects occurring while processing the chips. The global low yield in superconductor electronics (SCE) is due to the fact that little is known about the defects and fault mechanisms occurring in Nb technology. This is, however, of crucial importance in realizing the required complex systems with yields required for commercial production. For this purpose, a structural testing approach has been applied to the HYPRES Nb process. As a result, we have developed test structures for the detection of random defects in the process. Test chips were realized in the process and measurements were carried out. Test results on the processed chips leading to defect statistics in the HYPRES Nb process are presented in this paper.

Over the last decade, Monte Carlo simulations have emerged as the most useful way of predicting the yield of RSFQ circuits, as they consider all manufacturing tolerance effects on a circuit, and are not restricted to bias current variations. Here we finally present a comprehensive definition of layout-extracted Monte Carlo model creation for lumped-element Spice simulations-from the local and global values for inductance, resistance and junction area from statistical models, to the inclusion of parasitics, layer-to-layer variations, variations in the penetration depth, and capacitance and mutual coupling. Finally, the addition of bias current trimming to the simulations to compensate for most global variations is described, and comparative yield results listed.

We have designed and successfully tested at low speed a rapid single flux quantum signed serial multiplier-accumulator with target clock frequency 20 GHz. Each bit slice of the device consists of 106 Josephson junctions and 90 resistors. It consumes 22 mA of current and occupies 0.3 mm/sup 2/. The accumulator of the developed multiplier makes two (rather than three) primitive operations per cycle without any additional overheads. This makes it fast and very robust. In particular, /spl plusmn/18% bias supply margins have been measured in a four-slice multiplier. This is our first device where superconductor microstrip lines (MSLs) have been routinely used. The MSL interfaces introduce some overhead but it is compensated by the simplicity of the design procedure.

This paper discusses the possible modifications of the flux-flow oscillator, which is a part of an integrated receiver, for use as a precise clock oscillator in RSFQ circuits. At the price of losing tunability, the flux-flow oscillator can be used at resonance modes. To get higher clock rates, a parallel array of 20 identical under-damped Josephson junctions connected by superconducting micro-strip lines can also be used with an SIS mixer to form a phase-locked loop. The array shows a sharp resonance at 600 GHz, which can be used to make a precise on-chip clock. The linewidth of the emitted power of 150 kHz was estimated from the step differential resistance (free-run stability of 2.5 /spl middot/ 10/sup -7/). To convert frequency down to the desired level the array was matched to an over-damped pair of junctions, which form a precise frequency divider. The divider almost does not add any time jitter, thus the linewidth of 15 kHz can be achieved at 60 GHz. The clock stability can be improved by using an on-chip phase-locked-loop (PLL). The main part of the PLL is a phase detector, which can be based on an RSFQ Josephson sampler combined with an RSFQ fast counter. The suggested circuit probably could not compete with an SIS mixer, but significantly simplifies the circuit, and enables an on-chip RSFQ PLL closed by RSFQ frequency meter and DAC.

First-in, first-out (FIFO) buffers load and unload data using separate clocks that may be incoherent. We explore the application of FIFOs to circular shift registers, serial memory, and data re-clocking. We describe two different FIFO implementations in RSFQ. One employs classic handshaking using the Muller C-element. The other employs physical back-pressure based on repulsion of stored single flux quanta in a JTL. Both implementations use seven Josephson junctions, and a single bias resistor, per cell. The bias resistor can be reduced to an arbitrarily low value, thereby eliminating static power dissipation.

HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.

The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.

Several programs exist that calculate inductance in line structures. Some can even handle corners and holes in the ground plane. However, real structures in superconducting electronics are often more complex, and more elaborate techniques are needed to provide a reliable estimate of inductance, especially over very short intra-gate distances. A technique implemented with a modified version of FastHenry is discussed, whereby any inter-junction inductance in RSFQ circuits, in the vicinity of complex three-dimensional structures, junction cover pads and damping resistors, can be estimated. Placement of the reflection plane for the method of images is also discussed, together with the effect of segmentation size, and various results presented.

The SNS (Nb/HfTi/Nb) ramp junction technology process has been improved for digital superconducting circuit operation. DC interferometers were realized on an isolated superconducting ground plane, connections being realized through windows in the insulation layers. The inductances of superconducting Nb striplines (widths w down to the sub-/spl mu/m range) were measured. For a 250 nm SiO/sub 2//Nb-oxide insulation layer, the sheet inductances of striplines were determined at 0.382 /spl plusmn/ 0.009, 0.340 /spl plusmn/ 0.005, and 0.293 /spl plusmn/ 0.008 pH (stripline widths: 1.5, 1.0, 0.54 /spl mu/m) and compared with data calculated by different inductance evaluation programs. The Josephson junctions used in the interferometers exhibit a critical current density of j/sub C/=525 kA/cm/sup 2/ and a characteristic voltage of V/sub C/=95 /spl mu/V. The design of an RSFQ converter circuit was developed on the basis of SNS ramp junction technology. For circuit applications the critical current density j/sub C/ was set to 150 kA/cm/sup 2/.

The static frequency divider is commonly used as a performance benchmark for both superconductor and semiconductor digital device technologies. We present results of a static divide-by-two circuit, an NbN (1 kA/cm/sup 2/) SFQ T-flip-flop (TFF) operating to 97 GHz. Details of the measurement and operating criterion are discussed. Measurements of junction capacitance, a particularly important factor effecting device performance, are presented for TRW's NbN process. Simulations of expected device performance are shown to explain measured performance reasonably well. NbN results are presented alongside a those of a recent 8kA/cm/sup 2/ Nb divider operating at 300 GHz, as well as published Nb TFF results.

Josephson devices for superconducting electronic applications, such as RSFQ logic circuits and programmable voltage standards, require nonhysteretic junctions with a high speed or a high voltage resolution and hence with characteristic voltages spanning over several orders of magnitude. We present here our recent results on Nb/Al/Nb junctions where, by changing some fabrication parameters such as the thickness and deposition rate of the Al barrier, it is possible to obtain junctions with very different electrical properties. These junctions have characteristic voltages varying from a few tens of /spl mu/V up to more than 1 mV, with critical current densities from 10/sup 3/ up to 10/sup 6/ A/cm/sup 2/.

Superconducting bandpass delta-sigma (/spl Delta//spl Sigma/) modulators are being developed for direct analog-to-digital conversion of radio frequency signals in the GHz range. Recently we demonstrated operation of a superconducting bandpass /spl Delta//spl Sigma/ modulator with the highest center frequency (2.23 GHz) and sampling rate (up to 45 GHz) reported to date. The test chip used in that experiment includes an integrated acquisition memory, which eliminates the need for very high speed interfacing. This paper describes key implementation details of this complex test chip, which contains 4065 Josephson junctions. The paper also explains how magnetic coupling from large power supply currents can be reduced through the use of optically-isolated current sources with independent grounds. The measured output spectra of the modulator at a 45 GHz sampling rate are presented.

Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.

RSFQ circuit elements were fabricated based on the YBa/sub 2/Cu/sub 3/O/sub 7-x/ ramp-edge junctions and their characteristics were investigated. In particular, two types of interface circuits were designed, fabricated and their amplification functions were evaluated. The interface circuits comprised series array of SQUID's that shared a common inductor each other. Each SQUID was switched between zero voltage state and voltage state by current injection. Input signal was AC Josephson current for the type-one interface circuit. The input signal was an SFQ for the type-two interface circuit. Both interface circuits could successfully be operated. In particular, an output voltage more than 1 mV was obtained for the type-one interface circuit that comprised the stack of five SQUID's.

The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60 K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification.

The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.

Noise-induced bit error rate (BER) is an important design constraint for RSFQ circuits. No method, however, has been reported to calculate the BER of real, multi-junction RSFQ gates. We report such a method that requires only the operating margins and the root-mean-square noise current of the device in question. Noise current is determined using the ".ac" analysis card built into SPICE circuit simulators. As usual, operating margins are also determined using SPICE. These quantities determine BER via the error function, as is appropriate for threshold dynamics. The method is general enough to be applied to any RSFQ gate and even exotic circuits such as those that use passive microstrip signal propagation. Comparison to experimental data indicates that BER in RSFQ circuits does indeed arise strictly from thermal noise.

We recently reported communication up to 60 Gb/s between digital superconductor chips mounted on a passive carrier, using a novel driver circuit that produces a double-flux-quantum pulse. Here, we answer various practical questions pertaining to chip-to-chip and on-chip communication in greater detail. On-chip, the traditional single-flux-quantum driver is adequate, although margins and bit error rate degrade significantly at the microstrip resonance frequency. Chip-to-chip, using the double-flux-quantum driver, shows little frequency dependence, in spite of 13% reduction of signal current in the chip-to-chip transitions. Appropriate microstrip impedance is in the range 4-8 /spl Omega/ for a 4 kA/cm/sup 2/ Josephson junction IC process. Data includes bit errors rates for pseudo-random data in the range 3-27 Gb/s.

Niobium based rapid-single-flux-quantum (RSFQ) digital circuits generally operate at temperature 4 K. It is desirable to develop RSFQ circuits for operation at much lower temperatures, in particular to use as control and interface circuitry for superconducting qubits, and eventually for a full scale quantum computer. The total heat load is moderate - current designs generate 0.5 /spl mu/W per bias resistor, so simple RSFQ integrated circuits are easily compatible with commercial helium dilution refrigerators, and this power can readily be reduced by several orders of magnitude for complex future designs - but thermal conductivity will be a bottleneck. We present a simple model of heat flow through standard RSFQ structures. We find that circuits designed for 4 K operation can be used with little or no modification below one Kelvin. At lower temperatures however the heat generated on chip cannot be removed, and the temperature of a working circuit will rise. We suggest fabrication design rule changes to address this problem.

The practical implementation of RSFQ technology in most digital electronics application areas requires much more complexity than the presently developed circuits. There are two important issues in building large-scale RSFQ circuits: 1) the recycling of the bias currents and 2) the transfer of SFQ pulses between circuits located far apart. RSFQ circuits are well known to operate with DC current bias. Even though the DC current biasing is more forgiving than the problematic AC biasing, it can still be a big concern when the circuit size becomes large. Dramatic reduction of the total bias current can be achieved by biasing several RSFQ circuits in series, where each circuit is positioned on a separate ground plane. In this work, we have used magnetically coupled Josephson transmission lines as inputs and outputs of an isolated shift register to show the feasibility of using the concept of serial biasing in current recycling. The circuit was simulated, fabricated with Nb technology, and tested at a temperature of 4.2 K. Test results show that SFQ pulses were transferred into the shift register built on a separate ground plane, clocked through it, and sent out back to the circuit on the original ground plane. We also studied on how to transfer SFQ pulses over an extended length, an important issue in building large RSFQ circuits. We have designed the circuits to test our microstrip line and multichip module approaches. We designed, optimized, fabricated and tested the circuits. Test results show that SFQ pulses can be successfully transmitted over an extensive distance in a chip and between chips.

Recently we found that several simple SFQ circuits (normally used as ADC comparators) dramatically outperform conventional SQUIDs in time resolution and slew rate. For example, it is possible to reach a resolution of about a few percent of flux quantum by using a single-shot measurement that takes only a few picoseconds. All these SFQ circuits produce during each clock period only one bit of information that indicates whether the applied flux is larger or smaller the threshold. As a result it is natural to call them digital (or logic) SQUIDs. The new sensors can be used to detect a direction of the electrical current induced in a superconductor loop by the external field and digitally compensated by another SFQ devices. This composite device contains two kinds of digital components and also could be called a Digital SQUID. It has a limited practical value with a hundreds MHz clock rate. Fortunately, the clock frequency could be increased to tens of GHz. But in this case the third digital device (a decimation filter) should be added to filter out off-band noise and reduce the output clock frequency. The last device is rather similar to an ADC and also could be called a Digital SQUID. It is easy to show that the last Digital SQUID has a practically unlimited slew rate and dynamic range without suffering significant loss of energy sensitivity of the conventional two-junction SQUID.

We have proposed a cell-based design methodology for SFQ logic. circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and don't need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. In the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.

The manufacturing process of LTS RSFQ circuits is quite similar to that of the semiconductor chips, thus providing the possibility of an ultra high-density packaging similar to the modern semiconductor logic circuits. However, the miniaturization of the interconnects does not enhance their performance. The present work highlights the impact of the parasitic interactions between the superconductive interconnects on the correct logical functionality and the upper bias current margins of the LTS RSFQ circuits.

We discuss an anodization technique for a Nb superconductive-electronics-fabrication process that results in an improvement in critical-current-density J/sub c/ uniformity across a 150-mm-diameter wafer. We outline the anodization process and describe the metrology techniques used to determine the NbO/sub x/ thickness grown. In the work described, we performed critical current I/sub c/ measurements on Josephson junctions distributed across a wafer. We then compared the J/sub c/ uniformity of pairs of wafers, fabricated together, differing only in the presence or absence of the anodization step. The cross-wafer standard deviation of J/sub c/ was typically /spl sim/5% for anodized wafers but >15% for unanodized wafers. This difference in J/sub c/ uniformity is suggestive of an in-process modification from an unknown cause that is blocked by the anodic oxide. It is interesting that small junctions do not see an improvement in I/sub c/ uniformity - apparently the anodization improves only the J/sub c/ uniformity and not the variation in junction size. Control of J/sub c/ is important for all applications of superconductive electronics including quantum computation and rapid single-flux quantum (RSFQ) circuitry.

Novel logic devices in the RSFQ and COSL superconducting logic families are most often sub-optimal. Before such devices can be incorporated into physical designs, they have to be optimized for high theoretical yield, and preferably for highest possible yield. Even simple logic gates can contain numerous inductors, resistors and Josephson junctions. During optimization, it is often needed to adjust all the element values. The search space is therefore very large, and genetic algorithms have been used with success to optimize such gates. The conversion of circuit file to genome for the genetic algorithms is discussed, as well as fitness evaluation through Monte Carlo analysis. Results with both novel and existing logic gates are presented. Other optimization techniques are also discussed in comparison to genetic algorithms.

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

A number of new fabrication techniques are developed and optimized in order to fit the requirements of contemporary superconducting electronics. To achieve ultimate performance of integrated submm receivers with operational frequency of 1 THz, tunnel junctions with AlN tunnel barrier having a R/sub n/S value as low as 1 /spl Omega//spl mu/m/sup 2/ have been developed. High quality characteristics of Nb/AlN/Nb tunnel junctions with R/sub j//R/sub n/=16 and R/sub n/S=10 /spl Omega//spl mu/m/sup 2/ have been demonstrated. Electron Beam Lithography (EBL) in combination with Chemical Mechanical Polishing (CMP) has been incorporated to produce Nb/AlN/Nb junctions with 0.03 /spl mu/m/sup 2/ area. A new approach to obtain overdamped Nb/AlO/sub x//Nb tunnel junctions has been proposed and realized. The dependencies of the main parameters of novel junctions on the current density and circuit geometry have been studied. These junctions may have a good potential in Josephson junction arrays and Single-Flux-Quantum applications (RSFQ).

The bias current requirement for RSFQ circuits is about an ampere per thousand gates. High current increases the thermal load of cables into the cryostat, produces undesirable currents and fields on-chip, and makes efficient power supply difficult. Series-biasing has been proposed, whereby the circuit is divided into blocks powered in series. This requires floating ground planes for each block, and differential signal propagation across ground plane boundaries where the blocks communicate. We have demonstrated transmission of pseudo-random data across a differential link using two distinct approaches, based on magnetic and capacitive coupling. For each circuit, we have measured data rates up to 30 Gb/s and bit error rates down to 10/sup -10/. Bit error rates extrapolate to lower values. Inductive coupling was implemented in TRW's 4 kA/cm/sup 2/ Nb process, capacitive coupling in TRW's 8 kA/cm/sup 2/ process.

Devices of three types: magnetic pulse generators, read-out circuits, and digital circuits controlling them are needed to support scalable operation of quantum logic based on the Josephson junction qubits. The most natural framework for implementation of such a classical interface to quantum circuits is provided by the RSFQ technology . In this work, we argue, however, that specific qubit requirements can not be satisfied with the conventional RSFQ approach and describe the necessary modifications. We suggest a new structure of the pulse generator based on two long underdamped Josephson junctions which is characterized by the reduced power consumption and reduced output noise. We also show how to trade off power consumption and speed of the digital control circuits by using Josephson junctions with similar values of the shunt resistors but very different critical currents. Finally, we suggest a new read-out circuit which enables dynamic compensation of the backaction down to the level approaching fundamental quantum-mechanical limit.