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High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They include a brief description of each converter, tables and curves with relevant information, such as voltage gain, voltage stresses and component count, and the identification of the use of coupled inductor or transformer based on the analysis of dc magnetizing current. Moreover, theoretical analysis and experimental results on a 50 kHz and 200 W prototype of selected isolated SEPIC with voltage doubler cell are presented to validate the proposed topology and concept. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

This paper revisits the behavioral modeling of inductors used for Switch-Mode Power Supply (SMPS) design. A novel unified behavioral modeling for power inductors is herein proposed, which considers the DC current passing through the device and the equivalent applied voltage and switching frequency as model inputs, and the resulting peak-to-peak current ripple, total power loss and temperature as model outputs. The proposed behavioral modeling relies on simple analytical formulas, discovered from experimental measurements by using a multi-objective evolutionary algorithm. The resulting behavioral models allow to define the “Constrained Operating Area” of a power inductor, which describes the boundary area in the three-dimensional domain of switching frequency, DC current and equivalent voltage that can be applied to the component while maintaining its peak-to-peak current ripple, power loss and temperature within given limits. The experimental case studies presented in the paper eventually confirm the reliability of the proposed behavioral modeling approach and of the resulting models, in the assessment of the suitability of a given inductor and in the comparative evaluation among different inductors for a given SMPS application. [ABSTRACT FROM AUTHOR]

This paper presents various techniques to achieve high efficiency for the bidirectional Cascaded-Buck-Boost converter. This converter has the features of low voltage across the switches and positive output voltage. The objective of this paper is to optimize the magnetics design to reduce the total losses in a low power non-isolated DC-DC circuit. A rigorous loss model with component nonlinearities is developed to determine the power loss distribution. It is validated by simulations and experiments. Based on the results of the power loss analysis and due to the low inductor profile and high efficiency target, nanocrystalline material will be the best candidate. Therefore, a new small volume low profile planar-nanocrystalline inductor is designed. Various deep de sign aspects for core and copper are discussed. The Finite-Element-Analysis (FEA) method is used to examine and visualize the inductor design. By implementing the planar-nanocrystalline inductor, a California Energy Commission (CEC) weighted efficiency of 99.05% for the buck mode and 98.98% for the boost mode are achieved with a peak efficiency of 99.24% and 99.21%, respectively. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]

This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOM $_{\mathbf {T}}$ are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is $0.146\times 0.205$ mm $^{\mathbf {2}}$. [ABSTRACT FROM AUTHOR]

In this paper, a piecewise quadratic slope compensation technique for eliminating subharmonic oscillations in dc-dc switching converters is studied. With this technique, a self-generated signal is used in the compensation scheme resulting in a naturally full duty cycle stability domain. The expression of the piecewise quadratic compensating signal within a switching cycle is derived. It is obtained that the steady-state value of the amplitude of this signal is the same as in the conventional linear slope compensation scheme that guarantees stability for all values of the duty cycle. However, in the piecewise quadratic scheme this is achieved without exact knowledge of the inductance value nor sensing the input and the output voltages. The stability of the converter under the considered compensation scheme is also guaranteed for all values of the duty cycle with voltage loop open. A boost converter under peak current mode control is used to validate the theoretical results both by numerical simulations and by experiments. Simulation results are analyzed and compared to the performances of the state-of-art techniques with voltage loop closed. [ABSTRACT FROM AUTHOR]

Present universal serial bus (USB) battery chargers often suffer from limitations to meet the increasing demand for quick charging due to compromised power efficiency and complicated hardware implementation. In this paper, we propose a charge unifiable (QU) control scheme that enables a battery charger to improve power efficiency in a low-profile hardware manner. This scheme features fully soft-switching (vis-à-vis hard switching) and single control scheme (vis-à-vis multiple) for distinct constant current (CC) and constant voltage (CV) charging modes. To the best of authors’ knowledge, the proposed QU control scheme is the first to simultaneously offer fully soft-switching, innate CC-and-CV regulation, and seamless CC-to-CV transition. To verify the proposed design, we monolithically realize a low-profile high-efficiency fast battery charger based on this scheme. The prototype embodying a tiny 470-nH output inductor supports a maximum input voltage of 16V, output voltage of 2.2-4.2 V, output current of 0.1-2 A, and peak power efficiency of 96.2%. When benchmarked against state-of-the-art counterparts, the proposed charger features at least $2.1\times $ smaller inductor and 7.2% higher power efficiency at both the maximum and the minimum output power charging scenarios. Further, this charger is the only design that features ≥91% power efficiency in the whole load range. [ABSTRACT FROM AUTHOR]

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical equations describing the dynamic behavior. Numerical simulations from a detailed switched model validate the theoretical results and a good agreement is obtained. A boost converter prototype is built to validate the theoretical finding and the numerical simulations. It is observed that even when the analysis and the simulation predict zero inrush current, the experimental circuit still exhibits an unsuitable initial current peak and an unacceptable transient response during start-up. This phenomenon is mainly attributed to the presence of an unavoidable delay due to the computation time required by the digital control platform. The resulting inrush current is more pronounced in the presence of nonlinear load such as a CPL and saturable inductor. Some solutions are proposed to mitigate the inrush current problems. Simulations results taking into account the delay and experimental measurements demonstrate the validity of the proposed solutions. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper presents an inductor-less switched capacitor based energy harvester, which can simultaneously harvest from 2 energy sources (Solar + Piezo). The proposed harvester employs maximum power point tracking algorithm, by changing the conversion ratios of the charge pumps for piezo and solar sources, and output voltage control by varying the switching frequency. The proposed MPPT algorithm can match the input impedance of two sources simultaneously. Implemented in 65nm CMOS, the proposed harvester can generate a fixed output between 1.8 and 2.5 V output while delivering 35 $\mu \text{W}$ to 70 $\mu \text{W}$ power with a peak power conversion efficiency of 74.6%. [ABSTRACT FROM AUTHOR]

This paper presents a turning-point output voltage (TPOV) prediction method to enhance the reference tracking speed of buck converters for dynamic voltage and frequency scaling (DVFS) application. The optimal reference tracking is modeled, and the TPOV is formulated. The parasitic effects are compensated with the proposed calibration scheme. Reference tracking considering load current changes is evaluated with the proposed end-point determination method. Additionally, this work optimizes the feedback network for smooth loop transition, and incorporates the frequency-locking circuit and the error correction path to address the shortcomings of the hysteretic control. The prototype is fabricated in a 0.13- $\mu \text{m}$ CMOS process with a 1.2-V supply voltage. The converter achieves a near-optimum reference tracking over a wide range of output voltages, from 0.5 to 1 V. Various output voltage steps are measured for different load cases. For a 0.5–1-V output voltage step, with a 90-nH inductor and a 1- $\mu \text{F}$ output capacitor, the up- and down-tracking take 558 and 542 ns, respectively, matching the theoretical result of 533 ns. The prototype achieves a peak efficiency of 93.5%, and over 85% efficiency is measured with $\mathrm {V}_{\mathrm {O}}$ from 0.5 to 1 V and $\mathrm {I}_{\mathrm {O}}$ from 130 to 550 mA. [ABSTRACT FROM AUTHOR]

The recently-proposed dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is a promising approach for enabling the implementation of multiple fully-integrated power supplies with superior dynamic and cross-regulation performance in SoCs. However, switching the input and output stages at different frequencies raises many questions about the optimum strategy for controlling such converter topology. This paper explores and analyzes the various classes of controllers that can be employed in the output stage of the DF-SIMO buck converter topology, while taking account of key comparison metrics, such as circuit complexity, stability, steady-state and dynamic performance, and the range of operating conditions each controller may be suitable for. This includes average-based voltage-mode, ripple-based charge-mode, and ripple-based voltage-mode controllers. The predictions made by the analytical expressions derived for the various controllers are verified through system-level and transistor-level circuit simulations. [ABSTRACT FROM AUTHOR]

This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4–11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is −116.3 dBc/Hz and the corresponding FOMT and FOM varies from −180.96 to −191.86 dB and −172.6 to −183.5 dB, respectively. The VCO core area occupies only $0.1 \,\, \times 0.395\,\,\mu \text{m}^{{2}}$. [ABSTRACT FROM AUTHOR]

This paper presents an efficiency-enhanced low-profile zero-voltage-transition (ZVT) synchronous non-inverting buck-boost converter for 48-V tens-of-Watt output applications. By only using three auxiliary components shared between two switching nodes, zero-voltage switching (ZVS) of all four power switches and zero-current switching of the auxiliary switch are achieved in the proposed converter to minimize the switching power loss. Compared with the existing ZVT topologies, the proposed converter reduces the required number of auxiliary components, thereby decreasing the converter volume and power loss. In addition, the proposed converter can be configured into the buck mode with full ZVS capability to support a wide input range from 36 V to 90 V. Experimental results show that the proposed converter can operate at 1 MHz and deliver a maximum output power of 75 W. The measured peak power efficiencies achieve 92.5% and 96.3% in the buck-boost mode and buck mode, respectively. Compared with the state-of-the-art ZVS-based buck-boost counterpart, the proposed converter reduces the volume of the auxiliary circuit by ~2 times even with 28% increase in the maximum load current and two times reduction in the switching frequency, and provides higher peak power efficiencies in both buck-boost and buck modes. [ABSTRACT FROM AUTHOR]

A wide-input-range (5–115 V) current-accuracy-enhanced dc–dc LED driver is presented in this paper. A feedforward synchronous current control (FSCC) scheme is developed to improve the LED current accuracy over wide ranges of input and output voltages. In the FSCC, a reconfigurable valley current sensor is proposed to provide accurate positive and negative valley inductor current information for the controller corresponding to hard- and soft-switching modes, respectively. A dynamic peak reference generator is developed to automatically adjust the peak current reference value dependent on input and output voltages for reducing the deviations of the average LED current under different input voltages and numbers of output LED, thereby improving the current accuracy. Implemented in a 0.5- $\mu \text{m}$ 120-V CMOS process, the experimental results show that the proposed LED driver IC achieves a current accuracy within ±6.0% of the average LED current of 350 mA over an input voltage range from 5 to 115 V and numbers of series-connected LEDs from 1 to 25 by using only a small inductor of 10 $\mu \text{H}$. Compared with the state-of-the-art synchronous current control scheme, the variations of the LED current can be reduced by 2.3 and 4.2 times in the hard- and soft-switching modes, respectively, with the proposed LED driver using the FSCC. [ABSTRACT FROM AUTHOR]

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the high side and low side on-resistance according to the input voltage, is used. To maximize the output power, a maximum power point tracking circuit is designed to track the internal source resistance. Radio frequency (RF) kick-up and low voltage startup are used to improve the cold start voltage. The proposed converter is implemented in a 0.18- $\mu \text{m}$ standard CMOS process, which occupies a chip area of about 0.48 mm2. Measurement results show that the peak efficiency of the converter can be up to 90.8% and 60% at 180 and 20 mV of the open-circuit voltage, respectively. Owing to the cold startup circuit, the proposed converter can start successfully with 260-mV open-circuit voltage or −16-dBm RF input. Moreover, the open-circuit voltage can be further lowered to 12 mV with 1.5- $\mu \text{W}$ output power after startup. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a new method for detecting and reversing the polarity of a low-voltage thermoelectric generator (TEG) in inductor-based converters. The proposed technique makes use of the inductor response to a voltage change due to the flip in the TEG polarity. The inductor voltage provides two distinguishable states which correspond to the normal and the reversed TEG polarity. A switch matrix circuit is then used to correct the polarity by physically reversing the TEG connection. The detection circuit along with the switch matrix provide a positive input voltage from the TEG to the inductor-based converter. The proposed technique is an efficient polarity detection with all-digital implementation, fully integrated, small area and power overhead. The prototype chip is fabricated in 65-nm CMOS and occupies an area of 0.09 mm2. Measurement results confirm a maximum efficiency of 70% at 50 mV TEG voltage and 40~\mu \text A output current. The proposed technique is part of an autonomous thermal energy harvesting system that detects and corrects the TEG polarity. [ABSTRACT FROM AUTHOR]

This paper presents a piezoelectric energy harvesting circuit, which integrates a Synchronized Switch Harvesting on Inductor (SSHI) circuit and an active rectifier. The major design challenge of the SSHI method is flipping the capacitor voltage at optimal times. The proposed SSHI circuit inserts an active diode on each resonant loop, which ensures flipping of the capacitor voltage at optimal times and eliminates the need to tune the switching time. The diodes of the SSHI circuit are also used as a rectifier to further simplify the controller. The key advantage of the proposed circuit is a simple controller, which leads to low power dissipation of the proposed circuit to result in high efficiency. The proposed circuit is self-powered and capable of starting even when the battery is completely drained. The circuit was fabricated in BiCMOS 0.25~\mu \text m technology with a die size of 0.98 \times 0.76 mm2. Measured results indicate that the proposed circuit increases the amount of power harvested from a piezoelectric cantilever by 2.1 times when compared with a full bridge (FB) rectifier and achieves a power conversion efficiency of 85%. The proposed circuit dissipates about 24~\mu \text {W} while the controller alone only 1.5~\mu \text {W}$ . [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

A pair of universal current mode control schemes for charging a Li-ion battery for mobile applications are discussed in this paper. The peak-current mode control schemes, based on a single control loop, is universal because it is designed with a single-stage buck charger for both a conventional wall adapter dc source as well as a solar photovoltaic (PV) module of comparable specifications. The charging schemes remove the need for an extra MPPT (maximum power point tracking) power converter stage. This control scheme is non-linear and incorporates all possible scenarios: mode of operation of a battery, current charging rate and power characteristic of input source. The algorithm uses need-based MPPT and ensures minimal battery discharge, and also uses minimum number of sense variables in the circuit. The methods differ in the way MPPT is implemented: perturb and observe (P&O) and fractional open circuit voltage. Simulation results demonstrating battery charge profile, validity of the algorithm under varying insolation conditions and platform workloads are presented, along with a discussion of the trade-offs of the two methods. Proof-of-concept hardware results are also provided. [ABSTRACT FROM AUTHOR]

In this paper, loss mechanisms of monolithic high frequency Class-E PAs are studied. The switching behavior is analyzed to understand the discrepancy between common design equations and optimal design values as frequency scales up. Analytical results are verified by spice simulations. In addition, a design recipe based on loss analysis and effective output duty cycle is proposed for mm-waves PAs to boost their power added efficiency (PAE). The design approach is adopted to compare different technology nodes including the 130 nm, 90 nm, and 65 nm bulk CMOS. Newer technologies show better PAE only at the mm-waves regime. Simulations show that the PAE is boosted from 31% to 40% when the proposed design methodology is applied at 60 GHz using the 65 nm node. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

This paper proposes a fast transient quasi-V^2 fixed-frequency hysteretic buck converter designed and fabricated using TSMC 2P4M 0.35-\mum CMOS process. The proposed converter can achieve fixed frequency switching through a novel phase-locked-loop-based two-stage adaptive window control. Under ultralight load conditions, the proposed converter operates in a pulse frequency modulation mode to reduce the switching loss and improve light load efficiency. A quasi-V^2 technique is applied for obtaining inductor current information without relying on an output capacitor with a high equivalent series resistance; therefore, the output voltage ripple can be reduced. The experimental results show that the proposed converter can operate at a load current ranging from 18 to 700 mA, a supply voltage ranging from 2.7 to 4.2 V, and an output voltage of 1.2 V. The off-chip inductor and output capacitor are 2.2 \muH and 10 \muF, respectively. Through the PLL control, the switching frequency is maintained at 1 MHz. The transient response time is approximately 5 \mus, and the highest efficiency registered is 95.6%. [ABSTRACT FROM AUTHOR]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed inductor, duty-cycle, switch resistances and the class-E conditions at certain outphasing angle. Three different topologies are deduced from the proposed generalized model. The design equations for the circuit elements are derived analytically using the given class-E conditions. The overall outphasing performance is obtained numerically, and the optimum design settings are determined by the desired output power and efficiency characteristics. It will be shown that the proposed class-E OPAs can ideally maintain high efficiency (>80%) at 12-dB power back-off with a static square-wave drive signal. With 5-MHz UMTS downlink signal, the ideal average efficiency is more than 80%. The spectral and modulation requirements are satisfied when the predistortion is applied to the class-E OPA. [ABSTRACT FROM AUTHOR]

Power management of mobile digital systems-on-chip necessitates large voltage regulation performances. DC/DC converters used to supply digital cores are facing stringent constraints with respect to load transients, reference tracking and accuracy. The fast transient response offered by sliding-mode control is well suited to DC/DC converters with fast varying load. Fixed switching-frequency is also mandatory for EMI and noise related issues. Fixed-switching frequency sliding-mode control has been experimented as a multi-loop system. There is a necessity to investigate the stability when multi-loops interact and the parameter set for each loop is quite large. The paper details a methodology for the stability analysis of a frequency-controlled sliding-mode DC/DC converter. The proposed stability analysis takes the possible cross-interactions into account and can be used to optimise the DC/DC controller without the limitations of a non-interaction criterion. As a verification a DC/DC converter is implemented in CMOS 130 nm. Experimental results agree with the analysis main recommendations. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency zero-voltage- switching (ZVS) AC-DC light-emitting-diode (LED) driver. The structure of the proposed converter is based on a buck-boost power-factor-correction (PFC) converter. Through replacement of an output diode with a self-driven synchronous rectifier (SR), the conduction loss decreases significantly, and there is no switching loss because of the ZVS operation of the switching devices. In addition, no additional control circuit is required and cost reduction is achieved because the SR is self-driven. The efficiency of the proposed converter is higher than that of the conventional critical-conduction-mode (CRM) buck-boost PFC converter, owing to the reduced conduction loss of the high-side output rectifier and no switching loss of either of the switches. For verifying the ZVS operation and efficiency improvement of the proposed AC-DC LED driver, theoretical analysis and experimental results of a 48-[V] and 1.4-[A] prototype for LED driver are discussed. [ABSTRACT FROM AUTHOR]

In this paper we investigate the sine qua non condition of existence of equilibria for electrical systems with external (AC or DC) sources furnishing constant power to the loads, which is a scenario encountered in modern applications. Two general cases are considered, when the system is i) linear time-invariant or ii) nonlinear, with dynamic behavior described by a port-Hamiltonian model with constant dissipation and switching interconnection matrix. The latter class includes the practically important case of power converters. For both cases necessary and sufficient conditions for existence of equilibria are given, which give an upper bound on the power dissipated in steady-state that should exceed the extracted constant power. The existence of the equilibrium is ensured if and only if the inequality is satisfied. [ABSTRACT FROM AUTHOR]

The unprecedented interest in high bandwidth applications in the mm-wave range has set off a wave of research exploring techniques that enable wide tuning range voltage-controlled oscillators (VCOs). Low frequency CMOS LC-VCOs (< 10 GHz) have been well studied in the literature and several approaches have been developed to optimize their performance. However, there lie several interesting challenges in the mm-wave space, specifically close to the f_T/f\max, that motivate the need for analyzing the tuning range and phase noise in mm-wave VCOs. This paper presents a detailed analysis of the ultimate performance bound in simultaneously achieving low phase noise and wide tuning range in CMOS VCOs. The analysis is conducted on a 130 nm CMOS process, and confirmed by measurement results on three VCOs at 26 GHz, 34 GHz and 40 GHz. Finally, the impact of CMOS technology scaling (from 130 nm down to 45 nm), on the achievable performance bounds is analyzed and presented. [ABSTRACT FROM PUBLISHER]

A soft-switching bidirectional dc-dc converter using a lossless active snubber is proposed in this paper. In the proposed converter, zero-voltage-switching (ZVS) of main switches is achieved by utilizing an active snubber which consists of auxiliary switches, diodes, an inductor, and a capacitor. Although conduction losses associated with additional components increase, switching losses are significantly reduced due to the ZVS operation of main switches. Therefore, total efficiency is improved. Moreover, there is no reverse-recovery problem of the intrinsic body diodes of the switches. To verify the ZVS of the main switches and efficiency improvement of the proposed bidirectional dc-dc converter, theoretical analysis and experimental results from a 200 W prototype are discussed. [ABSTRACT FROM AUTHOR]

This paper presents analytical expressions for the sub-nominal operation, which is only the zero current switching (ZCS) condition, of the class-E power amplifier with a shunt inductor at any duty ratio. The duty ratio is considered not only as a design specification but also as an adjustment parameter. In the sub-nominal operation with any duty ratio, both the peak switch voltage and the peak switch current can be set as design specifications due to two more degrees of design freedom in comparison with the class-E nominal amplifier at the fixed duty ratio. Additionally, it is also seen that the duty ratio affects the maximum operating frequency and the output power capability with ZCS condition. A design example of the class-E ZCS amplifier with a shunt inductor under the specifications of peak switch voltage and peak switch current is given. The measurement and a simulation by circuit simulator results agreed with the analytical expressions quantitatively, which show the validity of our analytical expressions. [ABSTRACT FROM PUBLISHER]

Three types of bifurcations (instabilities) in the DC-DC converter under valley current mode control (VCMC) are analyzed, which is an extension of a recent paper on the peak current mode control (PCMC). The three bifurcations are border-collision, period-doubling, and saddle-node bifurcations. The corresponding critical (instability) conditions are derived. The derived conditions divide the parameter space into different operating modes. Contrary to the general belief that the critical conditions for VCMC and PCMC are symmetric with respect to the duty cycle D=1/2, most critical conditions are actually asymmetric. The dynamics symmetry is converter, bifurcation, loading, and parameter dependent, verified by bifurcation diagrams and time-domain simulations. The VCMC boost converter has rich dynamics and it is extensively analyzed. [ABSTRACT FROM AUTHOR]

This paper describes a time-limited power distribution control technique that can be used for single-inductor multiple-output (SIMO) DC–DC converter with many unbalanced loads. Furthermore, the true all-comparator control technique that raises no stability or complexity issues is proposed. This all-comparator technique for SIMO converters is realized only with a single shared hysteresis comparator at a constant switching frequency of 800 kHz. This leads to the development of a new inductor peak-current control technique that does not require compensators and a phase-locked loop. This converter is analyzed and compared with existing SIMO converters with respect to the requirements of next-generation power management ICs. The maximum efficiency of the converter reaches 92%. The fabricated chip supporting eight-channel outputs is implemented in a 0.35-\mu\ m CMOS process and occupies an area of 2.4\times 2.1\ \ mm^2. [ABSTRACT FROM PUBLISHER]

This paper describes a high switching frequency CMOS DC-DC converter employing phase shedding/segmentation and resonant gate drivers to improve light load efficiency. A novel output inductor network with positively coupled inductors between segments and negatively coupled inductors between phases is adopted in two-phase four-segment interleaved topology to improve effective inductance and reduce inductor current ripple. To limit the contribution of the gate driver to the total converter loss under light and medium loads, a new combined high-side and low-side resonant type gate driver with partially shared inductor is presented. The DC-DC converter is implemented in 0.18~\mum six-metal CMOS technology with 5 V power devices and occupies a total area of 2.55 mm \times 3.0 mm. It converts 4 V input to 1 to 3 V output with peak 1.78 A current under 100 MHz switching frequency. The measured peak efficiency is 77.4% at 5.95 W output power and the tracking mode bandwidth can reach up to 8 MHz. With resonant gate drivers, 5% efficiency improvement can be reached at 1 V output. Furthermore, the converter is able to maintain peak efficiency as the output current varies from 0.1 A to 1.86 A. [ABSTRACT FROM PUBLISHER]

Conventionally, inductor current is sensed and quantized before it can be used by digitally controlled DC-DC converters. These are intuitively done by using two separated functional blocks—an analog current sensor and an ADC. A few research works have investigated other ways of obtaining the inductor current information in the digital domain. This paper proposes an on-chip digital inductor current sensor that combines both the inductor current-sensing and quantization into a single functional block. In this way, the redundancies found in the conventional approach can be reduced and optimizations can be made to save chip area and power consumption. An 8-bit digital inductor current sensor has been designed and fabricated with a UMC 0.13~\mum CMOS process. The measurement results show that the digital sensor can provide digital inductor current information with a conversion time of 225 ns. This can be used by a buck converter with a switching frequency up to 4 MHz. The digital sensor has linear and monotonic input-output transfer curve properties with an LSB of 6.79 mA. It consumes current of 700~\muA at 1.2 V supply voltage. [ABSTRACT FROM PUBLISHER]

In this paper a digital amplitude modulator for a polar transmitter is presented. The instantaneous output power is modulated by adjusting the amplifiers load through a digitally controlled impedance transformation network. The modulator is suited for modulation schemes with moderate peak-to-average power ratio (PAPR), such as \pi/4 DQPSK. The modulator may also be used for fine gain control in constant envelope modulation schemes. A class E amplifier with digital impedance amplitude modulation is integrated in 90 nm CMOS. It achieves a peak output power of 9 dBm with a PAE of 30% when powered from a 1.2 V supply. The measured EVM is 2.6% for a 6 dBm \pi/4 DQPSK modulated signal with 2 Mb/s signal rate at 2.4 GHz RF frequency. [ABSTRACT FROM PUBLISHER]

This paper explores the subharmonic oscillation mechanism for constant on-time control, which has been widely used for power supply controllers in industry. As well as analyzing the stability criterion, this research reveals that the circuit propagation delay (\Delta t) can significantly increase the demand of ESR\cdot Co value for stable operation in practical applications. A thorough study is provided based on the inductor current information and the charge variations of the output capacitor. Thus, critical condition for subharmonic oscillation is derived, and the effect of circuit propagation delay is also quantified. Based on detailed analysis, a prototype with constant on-time control and added inductor current ramp is built. Experimental results verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new Class-E power amplifier (PA) with a \pi-matching output network. The PA is targeted at low output power wireless applications. Analytical formulae are derived to aid the PA design, characterization and optimization. A fully integrated 2.4-GHz PA for short distance communications has been implemented in 0.13 \mu\ m CMOS technology to verify the proposed design method. The measured output power levels vary from -3.2 to 5.7 dBm while achieving maximum overall efficiency of 55%. [ABSTRACT FROM AUTHOR]