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A subject and author indexes for the 2010 issue of "IEEE Transactions on Circuits and Systems Part I: Regular Papers" is presented.

In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2k feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures. [ABSTRACT FROM PUBLISHER]

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with $0.18\mu m$ CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the demodulator is able to demodulate the cycle-by-cycle modulated FSK signals with low modulation index of 2.5%, with a BER of $1.24\times 10^{-5}$. [ABSTRACT FROM AUTHOR]

This paper is concerned with bipartite tracking for double-integrator networked systems with signed communication graphs, where both cooperative and antagonistic interactions coexist. A finite-time bipartite tracking framework is established, where followers track either the state or the opposite state of a leader. Different from some conventional results with convergence over an infinite time horizon, the finite-time convergence in this paper is achieved in an accurate manner. Under structurally balanced signed graphs, an integral sliding mode based finite-time bipartite tracking controller is proposed. The construction of an integral sliding mode variable is to ensure that the system dynamics is driven onto a sliding surface in finite-time. On the sliding surface, neighbouring states are used together with the homogeneous technique to guarantee that bipartite tracking is achieved in finite-time. To further realize fixed-time bipartite tracking, a controller is designed by using the integral sliding mode and the bi-limit homogeneous concept. Finally, numerical examples are provided to demonstrate the effectiveness of the proposed controllers. [ABSTRACT FROM AUTHOR]

This paper presents a realization and implements techniques of 2-D linear time-invariant discrete filters described by a system function. Two classes are covered: finite- and infinite-impulse response systems with a separable denominator. This realization is based on a state-space approach, known as orthogonal filters, resulting in structures consisting of Givens rotations and delays. The techniques that are presented are illustrated by an edge detection system and a separable denominator band-pass filter designs. For the designed structures, magnitude errors caused by a finite precision arithmetic have been evaluated and compared with those obtained for direct structures based on difference equations. It has been shown that orthogonal structures possess lower magnitude errors. [ABSTRACT FROM AUTHOR]

Soft-input soft-output (SISO) detector for the iterative detection and decoding of coded spatial modulation (SM) signals needs to compute the extrinsic bit log-likelihood ratio (LLR) associated with each detected bit. The maximum logarithmic maximum a posteriori (max-log-MAP) detector is known to perform closely to the optimal logarithmic maximum a posteriori (log-MAP) detector with much lower computational complexity. In this paper, we first apply several mathematical tricks to derive a new and low-complexity algorithm for the max-log-MAP detector. The proposed algorithm features a new tree pruning technique to visit few lattice points and a smart list administration technique to retain a max-log-MAP detector. By following the proposed algorithm, we then design a hardware architecture for SISO detection of coded SM signals over the scenario of 64-QAM symbols, 8 transmit antennas, and 4 receive antennas. Under the TSMC 40 nm CMOS technology, the VLSI implementation results reveal that our architecture requires 46.4K gates and leads to detection throughput 450 Mbps, while operating at clock frequency 400 MHz and consuming power 46 mW. Being the first hardware architecture for SISO detection of coded SM signals, our proposed low-cost max-log-MAP detector is very attractive. [ABSTRACT FROM AUTHOR]

Exploring the use of fractional calculus is essential for it to be used properly in various applications. Implementing the fractional operator $D^\alpha $ in FPGA is an important research topic in fractional calculus; in the literature, only a few FPGA implementations have been proposed due to the memory dependence of the fractional order systems. In this paper, FPGA implementations of fractional order integrator/differentiator based on the Grünwald–Letnikov (GL) operator are proposed. Two algorithms are developed based on look-up table and quadratic and piece-wise linear approximation approaches to realize the GL operator and achieve high accuracy, better performance, and efficient usage of FPGA resources and to reduce the memory dependence of fractional order systems. The proposed work shows a maximum absolute error reduction of 91% compared with previous approaches. The proposed building blocks are used to implement a fractional order transfer functions for applications, including a Heavisides inductor-terminated lossy line system, a damped oscillator, a fractional order controller, and a fractional order V-shape multi-scroll chaotic system. [ABSTRACT FROM AUTHOR]

The emerging area of network science and engineering is concerned with the study of structural characteristics of networks, their impact on the dynamical behavior of systems as revealed through their topological properties, random evolution of networks, information spreading along a network, and so on. This area spans a wide range of applications in different disciplines. A topic of great interest in this area is the notion of network criticality. Most measures of network criticality are defined by the paths that flow through the nodes or edges. Since computing all the paths is computationally intractable, only the shortest paths are usually used for computing criticality metrics. Thus, measures that implicitly capture the impact of all the paths will be useful. The recently introduced concepts of the resistance distance and the Kirchhoff Index are two such measures. In this paper, we study these metrics and present several results that extend, generalize, and unify earlier works reported in the literature. In developing these results, the role of circuit theoretic concepts is emphasized. We also relate our works to Foster’s theorems and present a generalization that captures and retains the circuit theoretic elegance of Foster’s original theorems. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique based on the current steering technique for the generation of a reconfigurable current that approximates the linear, squaring, cubic, and exponential and their descending analog functions. The proposed implementation can be easily programmed to generate these functions by simply reconfiguring the weighting factors of current sources and offers an extendable input voltage range keeping excellent accuracy. The circuit topology has been fabricated using $0.18~\mu \text{m}$ TSMC CMOS process under 1.8 V supply voltage. Measurements results validate the theoretical analysis giving for 400 mV input voltage range while keeping small relative approximation errors, 0.3%, 1%, 1.9%, and 0.7% for linear, squaring, cubic, and exponential, respectively. [ABSTRACT FROM AUTHOR]

Polar codes have received increasing attention in the past decade, and have been selected for the next generation of the wireless communication standard. Most research on polar codes has focused on codes constructed from a $2\times 2$ polarization matrix, called binary kernel: codes constructed from binary kernels have code lengths that are bound to powers of 2. A few recent works have proposed construction methods based on multiple kernels of different dimensions, not only binary ones, allowing code lengths different from powers of 2. In this paper, we design and implement the first multi-kernel successive cancellation polar code decoder in literature. It can decode any code constructed with binary and ternary kernels: the architecture, sized for a maximum code length $N_{\max }$ , is fully flexible in terms of code length, code rate, and kernel sequence. The decoder can achieve a frequency of over 1 GHz in 65 nm CMOS technology, and a throughput of 615 Mb/s. The area occupation ranges between 0.11 mm2 for $N_{\max }=256$ and 2.01 mm2 for $N_{\max }=4096$. Implementation results show an unprecedented degree of flexibility: with $N_{\max }=4096$ , up to 55 code lengths can be decoded with the same hardware, along with any kernel sequence and code rate. [ABSTRACT FROM AUTHOR]

In this paper, conditions for checking the realizability of fractional-order impedance functions by passive networks composed of a fractional element (either a fractional capacitor or a fractional inductor) and some RLC components are derived. To this end, at first the newly obtained conditions for realizability of fractional-order impedance functions by a passive network composed of a fractional capacitor and some RLC components are extended to include the case that the polynomials involving in the impedance function can have roots on the imaginary axis. Then, the necessary and sufficient conditions are found on a fractional-order impedance function to be realized by a passive network composed of a fractional element and some RLC components. Furthermore, a procedure for finding the realization in the realizable cases is proposed. Finally, the realizability conditions for a special class of fractional-order impedance functions are simplified. [ABSTRACT FROM AUTHOR]

In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT. [ABSTRACT FROM PUBLISHER]

In this paper, we present a new fast Fourier transform (FFT) hardware architecture called constant multiplier (CM) FFT. Whereas rotators in previous architectures must rotate among several different angles, the CM FFT exploits the use of constant multipliers to calculate the rotations. The paper explores the 4-parallel and 8-parallel radix-2 CM FFT, which calculates the FFT entirely by using constant multipliers. Later, radices $2^{k}$ are presented, with emphasis in radix-24 and radix-25 as the best alternatives. Experimental results for a 1024-point radix-25 CM FFT show that the proposed approach reduces the number of block random-access memories (BRAM) and digital signal processing (DSP) slices with respect to previous approaches, while achieving the highest clock frequency for a 4-parallel FFT architecture on field-programmable gate arrays (FPGAs) reported so far. [ABSTRACT FROM AUTHOR]

In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction. [ABSTRACT FROM AUTHOR]

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within $77~\mu \text{s}$ , which translates to a 37% reduction in processing cycles from state-of-art. [ABSTRACT FROM AUTHOR]

The stability criteria based on the Rollett parameter ($K$) plus one auxiliary condition is yet the most popular method used by designers to evaluate the stability of a two-port network although other criteria are available. In this paper, novel analytical proofs of the criteria utilizing $K$ and a new geometrical proof of the relationship between the stability of the ports of a circuit are proposed. They are obtained by making use of relationships between the reflection coefficients at the ports of the network and novel expressions that bind stability circles and unit mapping circles. The developed relations make the proposed proofs easier and more immediate than the traditional ones. Moreover, a new auxiliary condition having the same complexity and a greater geometrical insight with respect to the traditional ones is used. [ABSTRACT FROM AUTHOR]

In this paper, we presented a method of minimizing the number of overlapped partial products in the accumulation of four-term Karatsuba multiplication. This method reduced the summation of 13 overlapped partial products to 9 and the summation of 40 overlapped partial products to 24 in the case of four-term Karatsuba multiplication and eight-term Karatsuba multiplication, respectively. Moreover, to deal with the problem of negative multiplicands introduced by the choice in the evaluation of four-term Karatsuba multiplication, we further presented a method of converting negative multiplicands to non-negative multiplicands. In this way, our method would lead to the reduction of summation complexity and not using signed multipliers. Compared to the original Karatsuba multiplication designs, our proposed Karatsuba-like multiplication with optimal interpolation would lead to up to 7.7% reduction in ADP (area-delay-product) in ASIC implementations, and up to 20.2% reduction in ADP compared with built-in designs of Synopsys Design Compiler. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low complexity architecture design methodology for fixed point root and power computations. The state of the art approaches perform the root and power computations based on the natural logarithm-exponential relation using Hyperbolic COordinate Rotation DIgital Computer (CORDIC). In this paper, any root and power computations have been performed using binary logarithm-binary inverse logarithm relation. The designs are modeled using VHDL for fixed point numbers and synthesized under the $TSMC 40$ -nm CMOS technology @ 1 GHz frequency. The synthesis results shows that the proposed ${ { N}}^{\text {th}}$ root computation saves 19.38% on chip area and 15.86% power consumption when compared with the state of the art architecture for root computation without compromising the computational accuracy. Similarly, the proposed ${ { N}}^{\text {th}}$ power computation saves 38% on chip area, 35.67% power consumption when compared with the state of the art power computation with out loss in accuracy. The proposed root and power computation designs save 8 clock cycle latency when compared with the state of the art implementations. [ABSTRACT FROM AUTHOR]

Generalized integrated interleaved (GII) codes allow localized decoding of short sub-codewords. They are essential to hyper-speed data storage, communications, and continued scaling of distributed storage. Sub-codewords, which are usually Reed–Solomon (RS) or BCH codewords, are nested to generate codewords of higher correction capabilities. If the decoding of individual sub-codewords fails, the higher-order syndromes from the nested codewords are utilized to correct more errors. GII decoder design faces many challenges. The major ones include: 1) high-speed nested decoding utilizing the higher-order syndromes; 2) efficient updating of higher-order syndromes after sub-codewords are corrected; 3) computation of nested syndromes and matrix inversion for converting them to higher-order sub-codeword syndromes; and 4) efficient architectures capable of addressing the variable correction capabilities of the nested codewords. This paper proposes novel algorithmic reformulations and architectural transformations to address each bottleneck. For an example, GII code that has the same rate and length as eight un-nested (255, 223) RS codes, the proposed GII decoder achieves more than seven orders of magnitude improvement in error-correcting performance with less than 30% area overhead compared to the RS decoder. With a critical path of seven XOR gates, the proposed decoder can easily achieve more than 40 GB/s throughput. [ABSTRACT FROM AUTHOR]

Approximate computing is an efficient approach for reducing computational costs. This method involves a trade-off between computational accuracy and the circuit’s power consumption, delay, and area. However, the accuracy requirements may differ for different applications. In some situations, precise results are required. Therefore, this paper proposes an accuracy-configurable radix-4 adder (ACRA), which uses the power gating technique to turn on or turn off the partial logic gates of an adder element dynamically to compute accurate or approximate results. When the ACRA operates in the approximate mode, the partial sum of one adder element is modified to reduce the error distance between the approximate and accurate results. A comparison of the ACRA with two state-of-the-art accuracy-configurable adders indicated that the ACRA achieved the best trade-off between the power–delay product and computational accuracy. In addition, in the image processing experiment conducted in this study, under half-approximate computation, the peak signal-to-noise ratio of the ACRA was less than 1 dB and its structural similarity index measure was maintained above 0.99. These results are superior to those obtained for other accuracy-configurable adders. [ABSTRACT FROM AUTHOR]

This paper presents a unified framework to generalize the traditional $k$ -core decomposition method for both weighted and unweighted networks. It not only subsumes previous $k$ -core decomposition methods but provides some new ones. With the help of the definition of $n$ -th order h-index, we prove that all $k$ -core indexes can be regarded as some steady state of h-index series with $n$ going to infinity. Furthermore, all $h$ -indexes we obtain in intermediate calculation steps can be used as ranking scores to assess node importance in networks. Finally, we apply the provided new methods as well as two existing ones to four real networks and compare their performances on spreading influences ranking. [ABSTRACT FROM AUTHOR]

This paper proposes a new switching sequence with the asymmetric placement of weighting elements for a unary digital-to-analog converter (DAC). The proposed sequence is based on a so-called knight’s tour according to the modified Warnsdorf’s rule. To estimate the efficiency of the proposed switching sequence, a 10-bit resistive DAC has been designed and fabricated in the UMC 180-nm technology. Experimental results show that in comparison with an array of weighting elements without compensation of the systematic error, the proposed switching sequence reduces the maximal integral (INL) and the mean INL by 20% on the average in the temperature range from −40 °C to 85 °C. Besides that, the maximal INL does not depend on the temperature, while the mean INL decreases with temperature increase. [ABSTRACT FROM AUTHOR]

In this paper, we formulate and prove new results in the context of storage functions for lossless systems: we use these results to propose new algorithms to compute the storage function. The computation of the storage function for the lossless case is not possible using conventional algebraic Riccati equation-based algorithms, though the storage function itself is well-defined. This is because a certain “regularity condition” on the feedthrough term in the i/s/o representation of the lossless system does not hold. We formulate new results about the storage function matrix for the lossless case and use them to propose non-iterative and stable algorithms to compute the storage function directly from different representations of the given system, namely, a kernel representation, transfer function, and the i/s/o representation of the system. Across the methods, for randomly generated transfer functions, we compare: 1) the computational effort (in flops); 2) the computation time using numerical experiments; and 3) the computational error. [ABSTRACT FROM AUTHOR]

This paper studies the fixed-order piecewise-affine (PWA) output-feedback control of PWA systems in an $\mathscr {H}_{\infty }$ setup. In particular, the conventional output-feedback closed-loop system is first augmented with the introduction of the input vector, and a descriptor presentation of PWA system is acquired. Then, a bounded real lemma is derived for the resulting PWA system, which is realized by the construction of a smooth piecewise Lyapunov function and application of the S-procedure. Furthermore, by availing oneself of the descriptor formulation, the fixed-order PWA output-feedback controller synthesis is carried out in a unified framework. An illustrative example is provided to show the efficacy and impact of the proposed control design methodology in a Chua’s circuit. [ABSTRACT FROM AUTHOR]

This paper aims at developing a systematic methodology for constructing continuous-time autonomous hyperchaotic systems with multiple positive Lyapunov exponents. To overcome the essential difficulty in balancing between local instability and global convergence, this paper initiates a new methodology for designing a dissipative hyperchaotic system with a desired number of positive Lyapunov exponents. A general design principle and the corresponding implementation steps are then developed. Three representative examples are shown to validate the proposed principle and implementation scheme. Moreover, a hyperchaotic circuit is constructed to verify a 6-dimensional hyperchaotic system with four positive Lyapunov exponents. Comparing with the traditional trial-and-error approach, the proposed method can design various hyperchaotic systems with any desired number of positive Lyapunov exponents in a systematic way. [ABSTRACT FROM AUTHOR]

This paper presents a hardware-efficient architecture for 4×4 and 8×8 high-throughput MIMO detectors. The adopted non-constant K-best algorithm tends to keep more survival nodes in top search tree layers and reduce computational complexity in bottom layers as opposed to the conventional K-best algorithm. A pipelined architecture is used to generate one detection output per clock cycle, thus meeting multi-gigabit throughput requirements for advanced wireless communication systems. The proposed efficient folding scheme strikes a suitable balance between complexity and throughput. This paper also presents a discussion on the scalability of this architecture with respect to the setting of QAM size, K values, and antenna number. One 4×4 MIMO detector IC has been manufactured and one 8×8 MIMO detector layout has been realized, both in 90-nm CMOS technology. The 4×4 detector IC has 232 kilogates (KG). Its maximum measured throughput is 4.08 Gbps at 170-MHz operating frequency and 1.3-V core voltage. The 8×8 detector has 665 KG. Its post-layout simulation results show that it achieves 4.37-Gbps throughput at 182-MHz operating frequency and 0.9-V core voltage. Compared to earlier hard-output detectors, both implemented detectors demonstrate good normalized power and normalized hardware efficiencies. [ABSTRACT FROM AUTHOR]

This paper proposes a high-performance bidirectional architecture for the quasi-comparison-free sorting algorithm. Our architecture improves the performance of the conventional unidirectional architecture by reducing the total number of sorting cycles via bidirectional sorting along with two auxiliary methods. Bidirectional sorting allows the sorting tasks to be conducted concurrently in the high- and low-index parts of our architecture. The first auxiliary method is boundary finding, which shortens the range for index searching by finding the boundaries of the range. The second auxiliary method is queue storing, which stores each useful index in a queue in advance to reduce the number of miss cycles during index searching. The performance of our architecture highly depends on the distribution of input data. For each set of input data to be sorted, five Gaussian distributions of the input data and four standard derivations for each distribution were adopted in our experiments. The results show that at the expense of some additional area cost, the number of sorting cycles and the energy consumption are significantly reduced by our method. [ABSTRACT FROM AUTHOR]

This paper addresses the fault detection problem for discrete-time Markovian jump systems with incomplete knowledge of transition probabilities, randomly varying nonlinearities and sensor saturations. For the Markovian mode jumping, the transition probability matrix is allowed to have partially unknown entries, while the cases with completely known or completely unknown transition probabilities are also investigated as two special cases. The randomly varying nonlinearities and the sensor saturations are introduced to reflect the limited capacity of the communication networks resulting from the noisy environment, probabilistic communication failures, measurements of limited amplitudes, etc. Two energy norm indices are used for the fault detection problem in order to account for, respectively, the restraint of disturbance and the sensitivity of faults. The purpose of the problem addressed is to design an optimized fault detection filter such that 1) the fault detection dynamics is stochastically stable; 2) the effect from the exogenous disturbance on the residual is attenuated with respect to a minimized \cal H\infty-norm; and 3) the sensitivity of the residual to the fault is enhanced by means of a maximized \cal H\infty-norm. The characterization of the gains of the desired fault detection filters is derived in terms of the solution to a convex optimization problem that can be easily solved by using the semi-definite programme method. Finally, a simulation example is employed to show the effectiveness of the fault detection filtering scheme proposed in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%. [ABSTRACT FROM AUTHOR]

This paper aims at solving the bipartite containment problem for linear singular multi-agent systems (MASs) with multiple dynamic leaders over general signed digraphs, where each leader can be autonomous or dynamically evolving via interactions with its neighboring leaders. To this end, we first establish some properties for the Laplacian matrices of signed digraphs. Then, three distributed observer-based bipartite containment protocols are proposed using different local output information. Multi-step algorithms for constructing the corresponding proposed protocols are also given. It is shown that under the proposed control protocols, bipartite containment can be achieved for any admissible initial states provided that the underlying signed digraph is weakly connected. Compared to the existing related works, the major contribution of present work is that the developed results are applicable for arbitrary weakly connected signed digraphs, no matter whether they are sign-symmetric or sign-asymmetric and whether they are structurally balanced or unbalanced. Two numerical examples are finally given to demonstrate the validity of our results. [ABSTRACT FROM AUTHOR]

Since the cache system has been a predominant part in modern SoC's and its capacity is sometimes larger than necessary for specific applications, it is desirable to enhance the role of the cache system to beyond its original purpose (performance improvement). In this paper we propose a versatile data cache, called DT (data/trace) cache, by making it to function simultaneously as a regular data cache and as a trace buffer for real time software debugging and monitoring. It is accomplished by modifying the cache organization such that a portion of the cache ways can be configured as a trace buffer during the run time. The trace buffer stores the trace produced by some trace generation hardware while the rest portion of the data cache keeps its original role. The trace can be dumped out using the existing cache write back circuitry. The integration of a DT cache with an instruction cache, an academic ARM7 processor and a trace generator has been accomplished at RTL level. The hardware overhead is very minor and does not impair the global critical path delay. For a 16 KB (8 ways, 512 lines, 8 words) DT cache with only 1 way as the trace buffer, it is capable of storing 12771 cycles of the program trace at the cost of merely 553 gates and slight increase in cache miss rate on the average. The experiments show that the DT cache is a highly cost-effective approach for real time on-chip trace buffering. [ABSTRACT FROM PUBLISHER]

Generalized spatial modulation (GSM), a special case of index modulation (IM), is a promising transmission scheme for the next-generation multiple-input-multiple-output (MIMO) communication network. By an encoding part of the information on the subsets of activated antennas, the GSM-MIMO is capable of achieving high energy efficiency with only a small number of radio-frequency (RF) chains. A modified computational efficient concentrated maximum likelihood (CECML) algorithm is first proposed to enable an efficient index sharing mechanism, which reduces computational complexity and facilitates parallelism for high-throughput detection. In addition, a joint subset QR preprocessing and successive interference cancellation (SIC) detection algorithm is developed to avoid matrix inversion operations in the minimum mean square error (MMSE) equalization. The proposed detector with QR preprocessing is capable of achieving near-optimal error rate performance as demonstrated by the numerical simulations. This paper also designed the GSM-MIMO detector chip based on the CECML-QRSIC algorithm for $4 \times 64$ GSM-MIMO systems with two active antennas using TSMC 40-nm CMOS technology. The synthesis and post-layout simulation results show that the proposed GSM-MIMO detection chip achieves a better normalized throughput, hardware efficiency, and energy efficiency than a previous SM-MIMO detector chip. [ABSTRACT FROM AUTHOR]

This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model. [ABSTRACT FROM PUBLISHER]

Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an $8\times 8$ AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a $16\times 16$ design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power. [ABSTRACT FROM AUTHOR]

In this paper two novel nonlinear cascade adaptive architectures, here called sandwich models, suitable for the identification of general nonlinear systems are presented. The proposed architectures rely on the combination of structural blocks, each one implementing a linear filter or a memoryless nonlinear function. All the nonlinear functions involved in the adaptation process are based on spline functions and can be easily modified during learning using gradient-based techniques. In particular, a simple form of the on-line adaptation algorithms for the two architectures is derived. In addition, we analytically obtain a bound for the selection of the learning rates involved in the learning algorithms, in order to guarantee a convergence towards a minimum of the cost function. Finally, some experimental results demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper develops a model predictive flocking control scheme for second-order multi-agent systems with input constraints. By penalizing both the control effort and the irregularity of the position distribution to a desired lattice formation, a decentralized controller is designed based only on neighboring measurements. Geometric properties of the optimal path are used to provide conditions guaranteeing convergence to a rigid \alpha-lattice flock avoiding inter-agent collision. Finally, numerical simulation is carried out to demonstrate the effectiveness of the proposed design. [ABSTRACT FROM AUTHOR]

This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multiple inputs required for row layered processing of hardware-friendly min-sum decoding algorithm. The results show good speed with lower area as compared to state-of-the-art circuits. Additionally, this work proposes dynamic multi-frame processing schedule which efficiently utilizes the layered-LDPC decoding with minimum pipeline stages. The suggested LDPC-decoder architecture has been synthesized and post-layout simulated in 90 nm-CMOS process. This decoder occupies 5.19 mm^2 area and supports multiple code rates like 1/2, 2/3, 3/4 & 5/6 as well as block-lengths of 648, 1296 & 1944. At a clock frequency of 336 MHz, the proposed LDPC-decoder has achieved better throughput of 5.13 Gbps and energy efficiency of 0.01 nJ/bits/iterations, as compared to the similar state-of-the-art works. [ABSTRACT FROM AUTHOR]

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths. [ABSTRACT FROM AUTHOR]

This paper proposes a novel decoding algorithm to enhance the throughput of turbo decoding in LTE-Advanced systems and its hardware realization. The proposed method completely removes the undesired phase-switching latency by partially overlapping in-ordered and interleaved decoding phases, and as a result, achieves a significant increase of decoding throughput. Moreover, the algorithm does not degrade error-correcting performance for high-rate codes which are essential to achieve the maximum data rate of LTE-Advanced systems. The proposed method called tail-overlapped decoding can be easily applied to the conventional parallel decoding architecture designed for standardized communication systems. In addition, a new structure for the extrinsic information memory is proposed to eliminate memory contentions. A 3GPP LTE-Advanced turbo decoder supporting both decoding methods is implemented in 0.13\mum CMOS technology to show the effectiveness of the proposed algorithm. The decoder exhibits a decoding rate greater than 1Gbps with six iterations, meeting the peak data rate of the LTE-Advanced standard with much less hardware complexity than those of the previous works. [ABSTRACT FROM AUTHOR]

This paper first presents a decomposition scheme to reduce the computation time and make the first-order moment-based cyclic convolution well suited for hardware implementation. By decomposing the fixed convolution kernel into similar subparts and using their preprocessing results as control signals, each subpart of cyclic convolution can be calculated with a basic computing substructure. Due to the flexibility of decomposition, a trade-off between computation time and hardware complexity exists. And for a pair of fixed decomposition coefficients, the similarity among subparts leads to the time-efficient structure and the area-efficient structure for cyclic convolution without limitation on the convolution length N and the word length L. Since the basic computing substructure only contains a simple control module, several circularly right-shift registers and N accumulation units, there is no requirement for multipliers and large memory. Comparisons in terms of area-delay product, area-time product and power consumption with the existing memory-based structures have been made to demonstrate the efficiency and effectiveness of the proposed structures. Using the same metrics, the comparison results further show significant improvement of the proposed designs over the previous first-order moment-based structure. [ABSTRACT FROM AUTHOR]

In this paper, a VLSI implementation of a complete MIMO channel equalization ASIC based on lattice reduction-aided linear detection is presented. The architecture performs preprocessing steps at channel rate and low-complexity linear data detection at symbol rate. Preprocessing is based on Seysen's algorithm for lattice reduction. We present algorithmic improvements of the lattice reduction preprocessing in terms of area and throughput of the VLSI implementation with minor impact on the error-rate. Due to the low-complexity implementation of the lattice reduction-aided data detection stage, our architecture is able to achieve very low power in typical packet-based MIMO wireless data transmission scenarios. The final 90 nm CMOS ASIC achieves an energy efficiency for the detection of 24 pJ/bit at a throughput of 720 Mbps with near-optimal error-rate performance. [ABSTRACT FROM AUTHOR]

This paper proposes a low-overhead space-time block code (STBC) interference canceller for high-mobility STBC-orthogonal frequency division multiplexing (STBC-OFDM) systems. The proposed STBC interference canceller combined with the two-stage channel estimator can be applied to wireless metropolitan area network (WMAN), like IEEE 802.16e system. At the vehicle speeds of 240 km/hr for 16 quadrature amplitude modulation (16 QAM), the bit error rate (BER)can be improved about 10 times of that just using the two-stage channel estimator. The proposed design is implemented in 90 nm CMOS technology. The gate count is 109.3 K, and the power dissipation is 1.45 mW at 83.3 MHz operation frequency with 1 V power supply. However, up to 61% hardware can be reused from the existed two-stage channel estimator design. After reusing, the proposed STBC interference canceller requires only 42.2 K gates, which is 4.9% overhead of the two-stage channel estimator. [ABSTRACT FROM PUBLISHER]

In this paper, Lyapunov stability and strong passivity are defined for nonlinear descriptor systems. The new concepts facilitate the formulation of the relationship between the stability and passivity of nonlinear descriptor systems. A Lyapunov stability theorem which describes a sufficient condition for the systems to be globally asymptotically stable and of index one is derived. By the Lyapunov stability theorem, the connection between Lyapunov stability and strong passivity is established. Furthermore, strong passivity of feedback systems is discussed and two passivity theorems are given. Using the given passivity theorems, strongly absolute stability of Lur'e type descriptor systems is discussed. The obtained strongly absolute stability criterion is shown to be more general and less conservative than the existing methods. Finally, two examples are used to illustrate the advantages and effectiveness of the obtained methods. [ABSTRACT FROM PUBLISHER]

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts: Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples illustrating the developed theory. [ABSTRACT FROM PUBLISHER]

Quantization is a prominent approach to compress model sizes of deep neural networks (DNNs), which clusters high-precision weights into a smaller set of quantization levels and represents high-precision weights by low-precision indexes. To achieve the same accuracy, nonuniform quantized DNNs (NUQ-DNNs) with unequal quantization intervals need lower index precision than uniform quantized DNNs (UQ-DNNs) with equal intervals, achieving smaller model sizes. Hence, deploying NUQ-DNNs on accelerators costs less on- and off-chip memory accesses than UQ-DNNs, which are more valuable for edge devices. However, accelerating NUQ-DNNs is nontrivial, since weight indexes cannot be directly used for computations. Previous NUQ-DNN accelerators adopt standard convolutions by decoding weight indexes into actual-weights multiplied with activations, causing abundant look-up overhead and redundant computations. In this work, we propose a weight-repetition-aware activation aggregating (WPAA) convolution approach to accelerate inference of variable-precision NUQ- and UQ-DNNs. By merging convolutions of multiple kernels, WPAA requires no look-up operation and removes redundant computations. Based on WPAA, we design a generic quantized DNN accelerator (GQNA). Furthermore, we propose a layer-adaptive kernel-reordering merging scheme to off-line adjust merging order of kernels for minimizing energy consumption of GQNA. Implemented under TSMC 28-nm technology, GQNA achieves 31.9 and 32.6 TOPS/W energy efficiency for 1-b UQ- and NUQ-VGG-16, respectively. [ABSTRACT FROM AUTHOR]

Look-up table (LUT) predistortion is the most promising technique to linearize RF power amplifiers (PAs). Before it can be employed successfully, loop delay errors must be estimated and compensated accurately. In this paper, the effect of loop delay errors on LUT predistortion is analyzed. It is shown that LUTs fluctuations happen to both amplitude and phase tables. Then, a novel loop delay estimation algorithm, with a high degree of robustness and accuracy, is presented. To further improve the robustness of LUT predistortion to loop delay errors, the smoothing filter (SMF) method to polish LUTs fluctuations is proposed here. LUT predistortion can suffer bigger loop delay errors because of the proposed SMF method, but retains good linearization performance close to the optimal one. The performance of the proposed loop delay estimation algorithm is investigated by comparative study with a state-of-the-art algorithm. Its robustness is also demonstrated under a noisy feedback path by simulations. The effectiveness of the SMF method is assessed by both simulations and experiments. Comparison among different predistortion systems is also presented. The results clearly show that the proposed techniques are useful for LUT predistortion. [ABSTRACT FROM AUTHOR]

The “sum of power of two (SPT)” is an effective format to represent filter coefficients in a digital filter which reduces the complexity of multiplications in the filtering process to just a few shift and add operations. The canonic SPT is a special sparse SPT representation that guarantees presence of at least one zero between every two non-zero SPT digits. In the case of adaptive filters, as the coefficients are updated with time continuously, conversion to such canonic SPT forms is, however, required at each time index, which is quite impractical and requires additional circuitry. Also, as the position of the non-zero SPT terms in each coefficient word changes with time, it is not possible to carry out multiplications involving the coefficients via a few fixed “shift and add” operations. This paper addresses these problems, in the context of a SPT based realization of adaptive filters belonging to the sign-LMS family. Firstly, it proposes a bit serial adder that takes as input two numbers in canonic SPT and produces an output also in canonic SPT, which is then extended to the case where one of the inputs is given in 2's complement form. This allows weight updating purely in the canonic SPT domain. It is also shown how the canonic SPT property of the input can be used to reduce the complexity of the proposed adder. For multiplication, the canonic SPT word for each coefficient is partitioned into non-overlapping digit pairs and the data word is multiplied by each pair separately. The fact that each pair can have at the most one non-zero digit is exploited further to reduce the complexity of the multiplication. [ABSTRACT FROM PUBLISHER]

This paper presents a design-oriented analytical approach for predicting fast-scale instability in power electronics converters under voltage-mode control strategy. This approach is based on the use of the ripple amplitude of the feedback control voltage as an index for predicting subharmonic oscillations in these systems. First, the work revisits the stability analysis technique based on the nonlinear discrete-time model, demonstrating that the ripple amplitude can be included within the expression of the Jacobian matrix of this model, hence giving a mathematical support to extend the ripple index to more complex topologies. A simple but representative buck converter under voltage-mode control is used to illustrate the approach. Using the ripple-based index, closed-form expressions of stability boundaries are derived. Unlike other available results obtained from existing methods, the stability boundary, in this work is expressed analytically in terms of both power stage and controller design parameters. Moreover, one can determine how these parameters are involved in the closed form expressions and, furthermore, how each parameter affects the stability of the system. The approach is validated by numerical simulations from the state equations and also experimentally within a wide range of the design parameter space. [ABSTRACT FROM PUBLISHER]

This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-2^4 SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations. [ABSTRACT FROM PUBLISHER]

The phase-response property for the bounded-input bounded-output (BIBO) stability of a two-dimensional (2-D) causal recursive digital allpass filter (DAF) with nonsymmetric half-plane (NSHP) support region is presented. Both cases of filters with real coefficients and complex coefficients are explored. Moreover, the effect of the numerator polynomial of a 2-D NSHP DAF on stability is also considered. The presented phase-response property has several applications. A remarkable application is that it can be utilized to enforce stability for a 2-D NSHP DAF design by choosing an appropriate phase specification. The eigenfilter design of 2-D NSHP DAFs for this application is also presented. Design examples are given to show these applications and the stability of a 2-D NSHP DAF is also inspected by the 2-D spectral factorization-based algorithm and a zeros-examining method presented by Ekstrom and Woods for confirmation. [ABSTRACT FROM AUTHOR]