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This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered and effectively modeled for the parasitics of the busbar, which is not accurate enough to evaluate the current imbalance for the busbar connected with SiC devices. This paper proposes accurate modeling of the effective parasitic parameter of laminated busbars with paralleled SiC MOSFETs. The model incorporates not only the self-inductance and resistance but also the complex mutual coupling effect of all the current paths. Moreover, a switching period is divided into two durations for accurate effective parasitic models, in which the busbar can have different effective models regarding one physical structure. Furthermore, for easy evaluation of the current balance, a single effective model, namely equivalent model, is derived for a physical structure by replacing the complex mutual network. A specific laminated busbar for EV inverter is analyzed to prove the above theory, which is validated by simulation and experiment separately. [ABSTRACT FROM AUTHOR]

Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive analysis of the intrinsic losses in hybrid envelope tracking power supply modulators used in envelope tracking power amplifier systems. The losses are computed entirely symbolically in terms of system parameters and a single design parameter. Resulting formulations are used to provide design insight into optimum biasing to minimize losses in a hybrid configuration, and establish the theoretical upper bound of achievable efficiency. To illustrate the value of this analysis, a Rayleigh distributed waveform is used to evaluate the performance of the hybrid modulator to describe OFDM and other complex modulation schemes. This paper demonstrates that the common convention of biasing the linear converter’s output stage to have zero average current is generally suboptimal from a loss perspective, and establishes how efficiency can be improved without modifying the underlying circuit topology. These findings are validated with a series of simulations modeling a hybrid modulator implemented in a 180-nm CMOS process. This paper derives for the first time, the intrinsic theoretical losses in the hybrid envelope modulator configuration. [ABSTRACT FROM AUTHOR]

To address the von Neumann bottleneck that leads to both energy and speed degradations, in-memory processing architectures have been proposed as a promising alternative for future computing applications. In this paper, we present an in-memory computing system based on resistive random-access memory (RRAM) crossbar arrays that is reconfigurable and can potentially perform parallel and general computing tasks. The system consists of small look-up tables (LUTs), a memory block, and two search auxiliary blocks, all implemented in the same RRAM crossbar array. External data access and data conversions are eliminated to allow operations fully in-memory. Details of addition, AND logic and multiplication operations are discussed on the basis of search and writeback steps. A compact instruction set consisting of 10 instructions is demonstrated on this architecture through circuit level simulations. Performance evaluations show that the proposed in-memory computing architecture is suitable for handling data-intensive problems. The average power consumption of the crossbar chip is estimated to be $45~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

In the memristive version of a standard space-invariant Cellular Nonlinear Network, each cell accommodates one first-order non-volatile memristor in parallel with a capacitor. In case, the resistance switching memory may only undergo almost-instantaneous switching transitions between two possible resistive states, acting at any time, as either the on or the off resistor, the processing elements effectively operate as first-order dynamical systems, and the classical Dynamic Route Map technique may be applied to investigate their operating principles. On the contrary, in case the memristors experience smooth conductance changes, as the bioinspired array implements memcomputing paradigms, each cell truly behaves as a second-order dynamical system. The recent extension of the Dynamic Route Map analysis tool to systems with two degrees of freedom constitutes a powerful technique to investigate the nonlinear dynamics of memristive cellular networks in these scenarios. This paper exploits this system-theoretic technique, called Second-Order Dynamic Route Map, to introduce a novel systematic procedure to design memristive arrays, in which a given memcomputing task is executed by ensuring that, depending upon the network inputs and initial conditions, the analogue dynamic routes of the states of the processing elements, namely capacitor voltages and memristor states, asymptotically converge toward pre-defined stable equilibria. [ABSTRACT FROM AUTHOR]

Owing to the flexibility of coupling structure, low standing losses and low Electromagnetic Interference (EMI), capacitive power transfer (CPT) has drawn much attention as one of the new wireless power transfer (WPT) technologies. However, to date, the load effect on the system performance has not been analyzed comprehensively, and the CPT system is usually fully tuned (tank network resonant frequency fully tuned to the fundamental components of the nominal switching frequency), which is challenging to maintain practically. Based on these considerations, this paper first provides a detailed analysis of how the load can affect the performance of a CPT system. An optimal load resistance is shown to exist for a CPT system with a non-fully/partially tuned LCC tank (tank network resonant frequency is designed to be lower than the fundamental components of the switching frequency). By dynamically transforming the load to its optimal value, the system can transfer maximum power to the load while maintaining zero voltage switching (ZVS) operation. Then, a controlled buck-boost converter based on perturbation and observation algorithm is introduced to the system to obtain the optimal equivalent resistance against the actual load variations via tracking the maximum power transfer point. The final prototype has demonstrated that a maximum power of 10 W is obtained, with an end-to-end power efficiency of about 70% over a wide range of load variations from $5~\Omega $ to 1 $\text{k}\Omega $. [ABSTRACT FROM AUTHOR]

This paper reviews the possibility of adding an active circuit that implements a small signal negative resistor, to the baseband portion of the N-path filter circuit, in order to compensate for losses that are caused due to harmonic products and other parasitic effects. By adding an active circuit inside the baseband part insertion loss can be eliminated reciprocally. Interestingly, in the case of two-port configuration, in addition to the improvement in insertion loss, a lower noise figure can be theoretically achieved as well. The introduction of the negative resistance is analyzed using linear periodically time-variant theory and linear time invariant approximation. The theoretical analysis is verified in simulation and measurement. The circuit implementation consists of a two-port N-path filter, implemented in a 65-nm CMOS process, with a PMOS cross-coupled pair serving as the negative differential resistor. We achieve $\sim 3.5~dB$ insertion loss improvement at the expense of $0.64~mW$ power addition, at the frequency range of 0.75–2 GHz. [ABSTRACT FROM AUTHOR]

The output ripple of switched-capacitor dc–dc voltage converter (SCVC) severely degrades the energy efficiency, performance, and robustness of the VLSI system. In this paper, a fully digital resistance modulation (FDRM) technique is proposed to reduce the output ripple of SCVC, which is scalable and compatible with the exiting ripple reduction methods. The proposed FDRM technique suppresses the impulsive charging and discharging effects in the SCVC operation by dynamically modulating its equivalent switch resistances, resulting in a reduced output ripple. The FDRM control signals can be generated from simple logic gates with the interleaved clock signals, realizing a low implementation complexity. The proposed FDRM technique was verified by a fully integrated SCVC in 180-nm CMOS process with an active area of 0.93 mm2. The measurement results show that the SCVC prototype with the proposed FDRM technique achieves an averaged ripple reduction of 31.6% and a peak conversion efficiency of 88.96% under a loading range of 95–190 $\mu \text{A}$. [ABSTRACT FROM AUTHOR]

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good speed and numerical stability. In this paper, the authors try to find a compromise between accuracy and computational costs, proposing a simulation procedure based on a linear approximation of the memristive device model. The description, formally derived from the traditional linear model, has been implemented in Verilog-A and, thanks to the analysis of practical design cases on a reference architecture, has been demonstrated to be useful in highlighting critical parasitic effects related to the interaction of the memristive cells with the memory circuit periphery. Thanks to the approximated method, a computer simulation time saving up to 40% is achieved when simulating a full cross-bar memory device. The model parameters have been extracted from experimental curves obtained from HfO2 devices implemented in a 250-nm BiCMOS IHP technology. [ABSTRACT FROM AUTHOR]

This paper deals with the global dynamical analysis of an H-bridge parallel resonant converter under a zero current switching control. Due to the discontinuity of the vector field in this system, sliding dynamics may take place. Here, the sliding set is found to be an escaping region. Different tools are combined for studying the stability of oscillations of the system. The desired crossing limit cycles are computed by solving their initial value problem and their stability analysis is performed using Floquet theory. The resulting monodromy matrix reveals that these cycles are created according to a smooth cyclic-fold bifurcation. Under parameter variation, an unstable symmetric crossing limit cycle undergoes a crossing-sliding bifurcation leading to the creation of a symmetric unstable sliding limit cycle. Finally, this limit cycle undergoes a double homoclinic connection giving rise to two different unstable asymmetric sliding limit cycles. The analysis is performed using a piecewise-smooth dynamical model of a Filippov type. Sliding limit cycles divide the state plane in three basins of attraction, and hence, different steady-state solutions may coexist which may lead the system to start-up problems. Numerical simulations corroborate the theoretical predictions, which have been experimentally validated. [ABSTRACT FROM AUTHOR]

Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves. [ABSTRACT FROM AUTHOR]

This paper describes simple, analytical expressions for a quadrature passive-mixer-based RF bandpass filter. We have analyzed the passive mixer clocked by the trapezoidal-shaped local (LO) signals with different rise and fall times. Obtained results show that the partially overlapping LO signals and/or large capacitance of low-noise amplifier load cause charge reduction of each baseband branch capacitance. This results in the filter characteristics degradation. To achieve good filter characteristics, short rise and fall time of the LO signal and/or appropriate mixer RF-node biasing is effective. Our analysis results agreed well with the data obtained from the Advanced Design System simulator. [ABSTRACT FROM AUTHOR]

This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars. The functions are realized as a netlist of NOR and NOT gates. Two alternate methods of evaluating the gates are used, serial and parallel, which give a tradeoff between the number of cycles and the size of the crossbar. A strategy for scheduling the gates to time steps has also been proposed to reduce the hardware overhead. The switching delays and energy requirements are estimated using SPICE simulation. Synthesis results are reported for ISCAS’85 benchmark functions that show an average reduction of 68.8% in the number of cycles, 52.8% in energy consumption, and 96.4% in the number of memristors required as compared to a very recently published work. [ABSTRACT FROM AUTHOR]

Every year, smarter and more complex attacks compromise electronic systems. Unauthorized access to the secure keys stored within nonvolatile memories is a concerning problem affecting secure applications. This paper presents an RRAM architecture secured against firmware and physical attacks. If a hack attempt occurs, and taking advantage of the threshold behavior of fast RRAM devices, this solution erases the whole memory in a single process preventing the sensitive information to be accessed while avoiding the circuit destruction. Complementing encryption solutions, our architecture provides extra-protection mechanisms that, even deprived from the main power supply, prevent the most sensitive information to be leaked. [ABSTRACT FROM PUBLISHER]

Emerging technologies have enabled efficient, high-speed realizations of ultra-dense crossbar arrays, driving the need for better insight in the transient operation of such systems. Previous work focused mostly on the effect of line resistance and its impact on steady-state response. In this paper, we develop a compact $RC$ framework that includes the effects of parasitics. We use memristors as an exemplar device where interconnect parasitics (resistance, inductance, capacitance, and conductance) are extracted using ANSYS Q3D extractor for 5- and 50- $nm$ feature sizes. A model for the crossbar is presented, considering the stray and coupling capacitive parasitics of the crossbar. The derived model is based on state-space representation and provides more insight into the behavior of crossbar arrays containing either linear or nonlinear switching devices. The framework provides a closed-form solution to evaluate Elmore delay, as well as the steady-state response of the system. Signal delay is evaluated and compared for both grounded and floating interconnect inputs and verified against HSPICE, showing a perfect match. [ABSTRACT FROM PUBLISHER]

This paper, split into Parts I and II, reviews recent innovations in circuit design that have accelerated the miniaturization of sensor nodes. Design techniques for key building blocks, such as sensor interfaces, timing reference, data communication, energy harvesting, and power management are reviewed. In particular, Part I introduces analog circuit techniques and sensor interfaces for miniaturized sensor nodes. The energy budget of such system is highly restricted due to the small battery volume. Therefore, ultra-low power design techniques are critical enablers and are reviewed. Design techniques for compact monolithic integration are also discussed. [ABSTRACT FROM PUBLISHER]

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- \mu \textm CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients. [ABSTRACT FROM PUBLISHER]

This paper presents a physics-based mathematical model for anionic memristor devices. The model utilizes Poisson- Boltzmann equation to account for temperature effect on device potential at equilibrium and comprehends material effect on device behaviors. A detailed MATLAB based algorithm is developed to clarify and simplify the simulation environment. Moreover, the provided model is used to simulate and predict the effect of oxide thickness, material type, and operating temperatures on the electrical characteristics of the device. The parameters of the proposed model are tuned and validated using experimental data of a fabricated wire based NbO1–x junction. This device is attractive for neuromorphic and computing applications, where multilevel state is desirable. The value of this contribution is to provide a framework intended to simulate anionic memristor devices using correlated mathematical models. In addition, the model can be used to explore device materials and predict its performance. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates the impact of variations in the senseamp and the reference voltage generation, and is based on switched-capacitor voltage boosters. The related area-performance-energy-resiliency tradeoff is explored, and design guidelines are derived to improve the read margin at minimum overhead. [ABSTRACT FROM PUBLISHER]

A frequently occurring subcircuit consists of a loop of a resistor (R), a field-effect transistor (FET), and a capacitor (C). The FET acts as a switch, controlled at its gate terminal by a clock voltage. There may be many such identical circuits connected in parallel, each driven by a different phase of the clock. This subcircuit may be acting as a sample-and-hold (S/H), as a passive mixer (P-M), or as a bandpass filter or bandpass impedance. In this work, we will present a useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. The SFG dissects the circuit into three filtering functions and ideal sampling. This greatly simplifies analysis of frequency response, noise, input impedance, and conversion gain, and leads to guidelines for optimum design. The analysis is extended to multi-path realizations common in RF applications. Part I of this paper focuses on the analyses of a single-path FET-R-C circuit's signal transfer characteristics. Part II extends these analyses to multi-path FET-R-C circuit configurations, which is followed by the noise and driving-point impedance analyses. [ABSTRACT FROM AUTHOR]

Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from \textrmPt/Ta2\textrm{O}5/\textrm{TaO}x/\textrm{Pt} RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of < 11% and a maximum error of < 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into \textrmTa2\textrm{O}5/\textrm{TaO}x RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM device performance at circuit level. [ABSTRACT FROM AUTHOR]

A novel Resistive random access memory (ReRAM)-based Compute-in-memory (CIM) macro is proposed to overcome the limited accuracy and throughput of a conventional ReRAM-based CIM macro that results from to the low R-Ratio and large variation of ReRAM. The proposed structure consists of 1T2R1C bit-cells and 4-kb ReRAM-based nvCIM architecture with ternary weight and ternary input. Ternary multiplication is implemented with voltage division between paired ReRAM devices within a bit-cell to make the output voltage variation tolerant and less sensitive to low R-ratios. An accumulation operation is realized with capacitive coupling so that linearity can be guaranteed for a large number of operands, allowing accurate and fast multiply-and-accumulate (MAC) operations. For comprehensive validation of the proposed CIM macro, the Verilog-A models for ReRAM devices with an adjustable R-ratio and adjustable variations are adopted to perform simulation on various R-ratio and variation conditions. With the peripheral circuits designed in 180-nm CMOS technology, the proposed CIM macro is confirmed to have high variation tolerance, high throughput, and less sensitivity to a low R-ratio, resulting in a high ternary DNN accuracy of 99.07% (0.01% drop) for the MNIST and 83.79% (0.38% drop) for the CIFAR-10 data sets with an R-ratio as low as 38 and 20%/40% low/high resistance variation. [ABSTRACT FROM AUTHOR]

This paper presents a design procedure of high-frequency loosely inductive coupled wireless power transfer (LIC-WPT) system based on class-E^2 dc-dc converter, taking into account the power loss reduction of inverter, coupling part, and rectifier simultaneously. Analytical expressions including the dc-to-dc efficiency of the WPT system are derived and the efficiency deterioration mechanism is explained by the circuit model. Through the analytical expressions, the design procedure for satisfying both the class-E switching conditions and power loss reductions at the coupling part is proposed from the circuit-theory viewpoint. The class-E^2 WPT system designed by the proposed design procedure achieves high dc-to-dc efficiency at low coupling coefficient, in particular, compared with those designed by the previous design strategies. The validity and effectiveness of the proposed design procedure were confirmed by PSpice simulations and circuit experiments. [ABSTRACT FROM PUBLISHER]

In this paper the power losses of efficient capacitive converters with multitude transfer ratio values are discussed. The loss mechanism circuits, based on general transposed series parallel (GTSP) topology, is studied and the losses are calculated, which in turn enables the “bottlenecks” to be identified and overcome. The calculations show that for a given number of switching cells the power losses of such converters are mainly dependent on the voltage conversion ratio, the topology function, the resistances of the switches in on and off states, the ESR of the capacitors, the switching frequency, the voltage drop, and the load. The theory explains the fact that was observed in experiments, that for low voltage conversion ratio values, efficiency decrease was measured. It is shown that for these low voltage ratio values the mechanism associated to the off resistance of the switches is more dominant and reduces the efficiency. This power loss estimation can be used as a powerful tool for the performance optimization of capacitive converters. The theoretical results are verified experimentally on a 10-cell GTSP converter prototype. The experimental results show good agreement with the proposed theory. [ABSTRACT FROM PUBLISHER]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/ $f$ noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/ $^\circ \text{C}$ supply and temperature sensitivity are obtained, respectively. [ABSTRACT FROM AUTHOR]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%. [ABSTRACT FROM AUTHOR]

This overview article describes Magnetoresistive Random Access Memory (MRAM) from a circuits and systems perspective. We discuss various tradeoffs and design challenges of MRAM in three broad application areas: 1) embedded non-volatile memory (eNVMs), 2) crossbar-based analog in-memory computing, and 3) stochastic computing. Certain MRAM characteristics, such as high retention, high endurance and fast read and write operations, make them ideal for replacing the standard CMOS memories for last-level cache applications with future scaling. However, various tradeoffs in power, performance and area pose conflicting requirements on MRAM design. We explore these challenges and various circuit techniques that have been developed to mitigate them. Further, we present various requirements of memristive crossbar arrays for accelerating matrix-vector-multiplication (MVM) operations in light of MRAM devices, and highlight various challenges, design considerations, and applicability of MRAM as crossbar arrays. Finally, we will elaborate on how inherent stochasticity of MRAM devices can be leveraged for implementing energy-efficient true random number generators (TRNGs) and stochastic units for performing certain tasks, such as developing fast solvers for combinatorial optimization, and stochastic neural networks. [ABSTRACT FROM AUTHOR]

This work presents a novel path balanced masked dual-rail pre-charge circuit design scheme based on binary decision diagrams (BDD), using one mask bit per output. It has been applied for achieving masked implementations of two common lightweight ciphers, namely Present and Lucifer. BDD based logic design is achieved using the CUDD tool and applying suitable variable reordering techniques. Path balancing has helped to counter the early propagation effect (EPE) to achieve a glitch free circuit design. Non-linear shift register has been used to generate the mask bits to avoid prediction of the mask bit, even if those should be occasionally uncovered. The design has been evaluated on many aspects such as glitch attack resistance, correlation / differential power analysis attack resistance, peak power variance, etc. and found to have satisfactory circuit performance while being highly robust to side channel attacks. [ABSTRACT FROM AUTHOR]

Bipolar resistive switching (BRS) cells based on the valence change mechanism show great potential to enable the design of future non-volatile memory, logic and neuromorphic circuits and architectures. To study these circuits and architectures, accurate compact models are needed, which showcase the most important physical characteristics and lead to their specific experimental behavior. If BRS cells are to be used for computation-in-memory or for neuromorphic computing, their dynamical behavior has to be modeled with special consideration of switching times in SET and RESET. For any realistic assessment, variability has to be considered additionally. This study shows that by extending an existing compact model, which by itself is able to reproduce many different experiments on device behavior critical for the anticipated device purposes, variability found in experimental measurements can be reproduced for important device characteristics such as I-V characteristics, endurance behavior and most significantly the SET and RESET kinetics. Furthermore, this enables the study of spatial and temporal variability and its impact on the circuit and system level. [ABSTRACT FROM AUTHOR]

Herein, we present a multi-energy harvesting interface integrated circuit (IC) that enables the efficient combination of heterogeneous power sources. An electromagnetic vibration energy generator (EVG) and a thermoelectric energy generator (TEG) are the two energy sources, which have quite different internal resistance (tens and kilo-Ohms). To solve the challenge of combining heterogeneous sources, we propose a current boost converter (CBC), which achieves the resistance transformation as well as the source type conversion. The challenge of realizing maximum power point tracking (MPPT) for each source is tackled by using a multi-task MPPT controller, which is efficiently shared between the two sources. To achieve energy harvesting under uncertain and random source conditions, we propose an input ($V_{\text {IN}}$)-dependent clock generator (VCG) and a vibration pulse detector (VPD). The VCG tracks the change of source conditions to generate the clock for the MPPT controller. The VPD allows tracking of the random amplitude and frequency changes of the EVG. The energy harvester is fabricated in a 0.18 $\mu \text{m}$ process with a thick top-metal option. Measured results show successful source detection, switching, and MPPT operation. The proposed IC provides an output power of up to 119 $\mu \text{W}$ with an end-to-end peak efficiency of 82% by consuming 582 nW. [ABSTRACT FROM AUTHOR]

An active electronic interface for maximizing the power extracted from a resonant piezoelectric vibration harvester by means of a multi-variable Maximum Power Point Tracking (MPPT) technique is presented. The input voltage of the electronic interface is dynamically adapted in order to ensure that the maximum power is extracted even if the vibration characteristics change with time. The digital control unit updates the amplitude, the phase and the frequency of such an input voltage without requiring the high-frequency sampling and elaboration of the harvester current or voltage. The unit exploits only the information on the vibration frequency kept from a small piezo accelerometer and a low-frequency sampling of the DC current. The implemented algorithm is as simple as the widespread Perturb & Observe algorithm, but it allows the extraction of significantly more power from the harvester. The power increase for a piezoelectric harvester with the proposed electronic interface is investigated both theoretically and experimentally. By using a commercially available piezoelectric harvester, the maximum power tracking performance of the proposed active interface is experimentally compared with that of a usual AC/DC converter with Perturb & Observe MPPT control. [ABSTRACT FROM AUTHOR]

The conditional switching of memristors to execute stateful implication logic is an example of in-memory computation to potentially provide high energy efficiency and improved computation speed by avoiding the movement of data back and forth between a processing chip and memory and/or storage. Since the first demonstration of memristor implication logic, a significant goal has been to improve the logic cascading to make it more practical. Here, we describe and experimentally demonstrate nine symmetry-related Boolean logic operations by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices, i.e., a particular device is switched depending on the state of another device. We introduce a family of four stateful two-memristor logic gates along with the copy and negation operations that enable two-input-one-output complete logic. In addition, we reveal five stateful three-memristor gates that eliminate the need for a separate data copy operation, decreasing the number of steps required for a particular task. The diversity of gates made available by simply applying coordinated sequences of voltages to a memristor crossbar memory significantly improves stateful logic computing efficiency compared to similar approaches that have been proposed. [ABSTRACT FROM AUTHOR]

A third-order passive switched-capacitor low-pass filter is presented together with experimental results. The current input-voltage output filter structure realizes complex-conjugate poles although it is composed of switches and capacitors. The results are verified with measurements performed on the filter prototype integrated in a 0.13- $\mu \text{m}$ CMOS technology. The prototype has a cut-off frequency of 470 kHz, 150- $\mu \text{W}$ power consumption from 1.2-V power supply, 92-dB SFDR, and an active area of 0.06 mm2. The switch-capacitor filter was obtained using a continuous-time model that is also described here and is useful for design, analysis, and simulation of oversampled switched-capacitor circuits. The model is applicable to a variety of topologies including multi-phase passive switched-capacitor filters, switched-capacitor integrators, as well as switched-capacitor dc/dc converters. [ABSTRACT FROM AUTHOR]

We introduce the cyclic switched-capacitor dc–dc converter for single-input multiple-output power delivery. We focus on applications in stacked voltage domain (SVD)-based systems, and show that the cyclic architecture is robust to load current mismatches. We analyze such converters and give intuition for their power losses. We give experimental results from an SVD based power management integrated circuit (PMIC), designed and fabricated in a 130nm CMOS technology. The PMIC is a combination of a 2/3 stage reconfigurable cyclic SC dc–dc converter and a linear regulator. It can drive $3\times 3$ mA loads with the input supply voltage varying from 2.35–3.65V. [ABSTRACT FROM AUTHOR]

An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled crystal oscillator using the proposed start-up technique in 90-nm CMOS is presented. Thanks to the dynamically adjusted load, the negative resistance is boosted, achieving a $13\times $ start-up time reduction and an overall power of $95\mu \text{W}$ for a 24-MHz crystal oscillator at 1 V. A fully autonomous feedback loop detects the oscillators envelop and adjusts the load capacitance at start-up. Thanks to the low-power start-up circuits, both the start-up time and the start-up energy are reduced. In addition, the robustness and versatility of the proposed method is verified by measuring quartz crystals with different frequencies and quality factors, as well as measuring against temperature, supply voltage, and load capacitance variations. [ABSTRACT FROM AUTHOR]

In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage ( Vdd ) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome Vdd scaling bottleneck, an efficient framework for Vdd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector ( Vdd , VBB ,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology. [ABSTRACT FROM AUTHOR]

As process technology downscales, read reliability has become a critical barrier for spin transfer torque magnetic random access memory (STT-MRAM), owing to the increasing process-temperature-voltage (PVT) variations, decreasing critical switching current of magnetic tunnel junction (MTJ) and supply voltage. To deal with the read reliability challenge, we propose herein a dynamic dual-reference sensing (DDRS) scheme. The key features of the proposed DDRS scheme include: (a) two reference signals, generated by two reference cells with the same structures as those of the data cells, are provided to the sensing circuit; (b) the reference signals are adaptively dynamical depending on the content stored in the target data cell; (c) two output signals are obtained to decide the sensing result, adding redundancy for supporting self-error detection (SED) capability. The proposed DDRS scheme can achieve a great improvement in sensing margin (SM) and bit error rate (BER), in comparison with conventional sensing schemes. In addition, no regularity problems exist in the proposed DDRS scheme, as the reference cells maintain exactly the same structures as those of the data cells. Our simulation results show that the proposed DDRS scheme can achieve a $\sim 7\times $ increase in average SM, and a ~ 70% reduction in average BER, compared with conventional sensing schemes. [ABSTRACT FROM PUBLISHER]

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation. [ABSTRACT FROM PUBLISHER]

An FPGA-based instrument with capabilities of on-board oscilloscope and nanoscale pulsing (70 ns @ \pm 10 V) is presented, thus allowing exploration of the nano-scale switching of RRAM devices. The system possesses less than 1% read-out error for resistance range between 1 \text{k}\Omega to 1 \text{M}\Omega$, and demonstrated its functionality on characterizing solid-state prototype RRAM devices on wafer; devices exhibiting gradual switching behavior under pulsing with duration spanning between 30 ns to 100 $\mu$ s. The data conversion error-induced degradation on read-out accuracy is studied extensively and verified by standard linear resistor measurements. The integrated oscilloscope capability extends the versatility of our instrument, rendering a powerful tool for processing development of emerging memory technologies but also for testing theoretical hypotheses arising in the new field of memristors. [ABSTRACT FROM PUBLISHER]

Extensive power management analysis of an inductive power delivery system for medical implants with a 1X/2X reconfigurable rectifier is conducted to help achieve higher system voltage gain and higher system power transfer efficiency under different loading and coupling conditions. Input capacitance matching due to mode switching is analyzed and a matching compensation scheme is proposed. Analysis results could then be used to guide the design of the inductive power delivery system that employs the reconfigurable rectifier. The 1X/2X reconfigurable rectifier was fabricated using a 0.13 \mum CMOS process. Measurement results verify the correctness of the analysis and demonstrate the effectiveness of the matching compensation method. [ABSTRACT FROM AUTHOR]