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In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

On the emerging development of SiC MOSFET, the switching frequency of power converters has been pushed to the order of hundreds of kilohertz or even megahertz to improve power density. However, the state-of-the-art simulations for such high-frequency power electronics circuits are usually time-consuming, blocking the studies of long dynamics such as several seconds. What’s worse, adopting physical models to simulate the turn-on and turn-off transients leads to high stiffness and therefore convergence problems. In this paper, an event-driven approach is proposed to improve the solving speed and simulation stability of SiC based high-frequency converters. A time-scale hierarchical automaton is proposed to model the system, where piecewise analytical transient model for SiC MOSFET is established as the second layer in the automaton to simulate the switching transients with improved numerical stability. Simulation of the system is driven by discrete events in the automaton. A 3.3 kW 79.1 kHz wireless power transfer system for the wireless charging of electric vehicle is studied. Compared with ideal switch model in Simulink and physical switch model in LTspice, 60-fold and 400-fold increases in terms of simulation speed with same level of accuracy are achieved respectively. The simulated results are also attested to by experimental verifications. [ABSTRACT FROM AUTHOR]

We present a compact, continuous, and numerically stable version of a tantalum oxide (TaOx) memristor model which can be employed for robust and reliable simulations of large scale memristor based circuits. The original model contains a piecewise differentiable function in the memductance expression and discontinuous step functions in the state equation. Additionally, the original model does not set a proper upper bound for the state variable and may admit blowing up solutions due to an exponential power term, preventing the use of it for numerically reliable simulations. Considering these drawbacks, we modify the original model so as to i) simplify the memductance function while removing its piecewise differentiable nonlinearity, ii) include a proper window function for the ON state dynamics, which is missing in the original model, iii) modify and bound the exponential power term to prevent an uncontrollable blow-up of the solutions, and iv) apply a process called unification, allowing us to remove the step functions inherent in the model, which is a novelty in state-limited memristor models. We validate the accuracy of the proposed model via DC and transient simulations, dynamic route map analysis and a Spice implementation of an anti-series configuration, showing the applicability of the model. [ABSTRACT FROM AUTHOR]

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design. [ABSTRACT FROM AUTHOR]