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Eight-switch three-phase post-fault inverter (ESTPI) is widely used as the reconfigured topology of three-phase three-level neutral point clamped DC/AC inverter when open-circuit fault occurs. A key technical challenge for the ESTPI is the post-fault controller design. The existing post-fault control approaches for the ESTPI suffer from the difficulty in trading off the current tracking performance, neutral point voltage (NPV) balancing and common mode voltage (CMV) levels. To solve this problem, this paper proposes an improved predictive current control algorithm. The proposed algorithm contributes to achieve accurate output current tracking while greatly reducing the CMV with a balanced NPV. Simulation and experimental results are presented to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

A 0.9-V $\Delta \Sigma $ modulator integrated into a 0.18- $\mu \text{m}$ CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (multistage noise shaping) architecture based on an adder-less feedforward structure is proposed. The proposed modulator has a unity signal transfer function in both stages of the modulator in order to reduce the integrator’s output swings. To mitigate the failure of slow process corner in the weak inversion as well as to further diminish the power consumption of the presented modulator, a fully differential self- and bulk-biased inverter-based operational transconductance amplifier is proposed. Experimental results are shown to demonstrate the efficiency of the proposed $\Delta \Sigma $ converter, showing state-of-the-art performance, by featuring 88.7-dB signal-to-noise ratio, 86.4-dB signal-to-noise plus distortion ratio, and 91-dB dynamic range within a signal bandwidth of 20 kHz, with a power dissipation of $103.4~\mu \text{W}$ when the circuit is clocked at 5.12 MHz. [ABSTRACT FROM AUTHOR]

Strong physical unclonable function (PUF) transcends the limitations of legacy secure key storage methods as emerging security primitive for cryptography and device identification/authentication. In this paper, a new low power and reliable mono-stable strong PUF is proposed. Its primary entropy is derived from the process variations of the parallel diode-clamped single inverter ring working in the subthreshold region. Due to manufacturing process variations, the mono-stable state of the output voltage of single inverter ring is Gaussian distributed around the half $V_{\text {dd}}$ point. The spread of the Gaussian is broadened by mixing it with another Gaussian distributed trip point obtained from a diode-clamped parallel inverter stage. As the main entropy of the raw response bits is derived from a mono-stable circuit, it has greater immunity to perturbances introduced by operating environments. In addition, as the mono-stable state for the output voltage is a non-linear combination of individual inverter rings, the resilience against machine learning attacks can be improved. The prototype chip was fabricated using a commercial 40-nm CMOS technology. The measurement results show that the power consumption of the 64-bit mono-stable PUF is merely $3.85~\mu \text{W}$. The native bit error rate is <8% at 0.9 ~ 1.3 V and −40~ 90°C, which can be further reduced to <1% using the proposed thresholding technique. The proposed PUF reduces the accuracy of support vector machine and reliability-based covariance matrix adaptation evolution strategy attacks by $36{\times}$ and $75{\times}$ , respectively, over that of arbiter PUF. [ABSTRACT FROM AUTHOR]

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

Ring oscillator (RO)-based physical unclonable function (PUF) is an emerging hardware security primitive but its response reproducibility is susceptible to changes in operating conditions and device aging. Present solutions to increase RO PUF reliability either incur large hardware overhead or require sophisticated RO selection algorithm. This paper exploits the optimal biasing of current starved (CS) inverter for the design of RO PUF with very high reliability against both temperature and voltage variations. With two additional transistors, the CS inverter can be adaptively biased at idle time and in active mode to significantly reduce the overall stress, making the proposed CS RO PUF robust against both environmental condition variations and aging. Without using error correction code, the reliability is further improved by a low-cost proximity detector circuit with a small sacrifice on challenge-response pair space. The correlation between successive RO pairs of different input challenges is also broken by an irregular clocking of the linear feedback shift register used to encipher the input challenges. Based on Monte Carlo simulation in TSMC 40-nm CMOS process, the reliability of native PUF responses has been raised substantially from 89.78% for the regular RO PUF to 95.88% for the proposed CS RO PUF over a broad temperature range of −40°C to 120 °C and ± 20% supply variation. With the proximity detector, the proposed Aging-resistant Current-starved RO (ACRO) PUF can attain 100% reliability statistically by discarding 34.47% fewer challenge-response pairs than the regular RO PUF. It is also ~3.7x more aging resilient than existing aging-resilient RO PUFs with ~2.38x lower power dissipation. [ABSTRACT FROM AUTHOR]

Scaling down the supply voltage (Vdd) below the transistors threshold voltage (Vth) has become a very popular technique in designing Ultra-Low-Power circuits whose demand has dramatically increased in the last few years. Designing these kinds of circuit is still a challenge, especially when the latest advanced process technologies are employed. The well-known design methodology used in the typical super-threshold domain (Vdd>Vth) cannot be applied to the design of a sub-threshold circuit due to the different transistor current-voltage relationships that hold when Vdd

In this paper, a simple approach to reduce delay variations in domino logic gates is proposed. Previous analysis by the same authors showed that delay variations in domino logic are mainly due to the feedback loop implemented by the keeper transistor and the output inverter gate. Accordingly, the proposed strategy aims at reducing the loop gain associated with this feedback loop, and hence its impact on delay variations. In particular, a simple modified keeper is proposed to reduce the loop gain while keeping the same silicon area, noise margin, and nominal performance. The resulting delay variations associated with keeper insertion are shown to be lowered by approximately 50%. The proposed approach is assessed by means of simulations in 65-nm and 90-nm commercial CMOS technologies. [ABSTRACT FROM AUTHOR]

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97∼dBc in-band phase noise, - 38∼dBc/Hz integrated noise, and 740 ns settling time. [ABSTRACT FROM AUTHOR]

This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25- µm CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results are presented for an MCML inverter and a ten-stage ring oscillator operating at supply voltages below the threshold-voltage value, with power consumption on the order of nanowatts. At a 300-mV supply, the oscillator works at a frequency of 638 Hz with a total power consumption of 345 pW. [ABSTRACT FROM AUTHOR]

In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-µm CMOS process parameters, and a reference simulation in 0.18 µm is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-µm process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations. [ABSTRACT FROM AUTHOR]

This paper presents an analysis of Class D inverter when irregular driving patterns are given to the gate drive of the switch devices. The analysis has been carried out with focusing on the waveforms, harmonics, low-frequency components, output power, and equivalent dc resistance, which are numerically analyzed and discussed. Class D inverters with six different Q factors from 0.1 to 20 are analyzed about 216 driving patterns for each Q. Superior four models of the six inverters are built and tested in circuit experiments. The calculated waveforms are compared to the experimental results. Both of them are agreed well in time domain and frequency domain. Analytical results show a possibility of a novel control method with irregular driving patterns. In spite of discontinuous control, the output power or voltage can be strictly changed as if continuous using the selected driving patterns in some ranges. [ABSTRACT FROM AUTHOR]

A multistage power CMOS-transmission-gate-based (CMOS-TG) quasi-switched-capacitor (QSC) boost dc-ac inverter is proposed and integrated with a boost dc-dc converter for a step-up application with ac or dc load. In this paper, using CMOS-TG as a bidirectional switch, the various topologies can be Integrated In the same configuration for achieving two functions: boosting and alternating; boosting for getting a sinusoidal output in which the peak is the result of a many times Step-up of the input; alternating to realize the positive/negative half sinusoidal of the output. The inverter does not require any inductive elements as inductor and transformer, so integrated circuit (IC) fabrication will be promising for realization. By using the state-space averaging technique, the large-signal state-space model of the inverter Is proposed, and then both the static analysis and dynamic small-signal analysis are derived to form a unified formulation for inverter/converter. Based on this formulation, there are presented for theoretical analysis/control design, including steady-state power, conversion efficiency, voltage conversion ratio, output ripple percentage, capacitance selection, closed-loop control and stability, and total harmonic distortion (THD), etc. Finally, a six-stage QSC boost dc-ac inverter is simulated by PSPICE, and the simulations are discussed for some cases, including: 1) steady-state ac output, ripple percentage, and power efficiency; 2) transient response of the regulated inverter for load variation; 3) a practical capacitive load: electromagnetic luminescent (EL) lamp, and 4) efficiency, ripple percentage, and THD for different loads. The results are illustrated to show the efficacy of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a new control scheme for a Class DE inverter, that is, frequency modulation/pulsewidth modulation (FM/PWM) control. Further, the FM/PWM controlled Class DE inverter is analyzed and we clarify performance characteristics. Since the FM/PWM controlled inverter has two control parameters, namely, the switching frequency and the switch-on duty ratio, it has one more degree of freedom for the control than the inverter with the conventional control scheme. The increased degree of freedom is used to minimize the switching losses. Therefore, it is possible to control the output power with high power-conversion efficiency for wide-range control. Carrying out the circuit experiments, we confirm that the experimental results agree well with the theoretical predictions quantitatively. For example, the proposed controlled inverter can control the output voltage from 56% to 191% of the optimum one, which is designed for 1.8 W at 1.0 MHz, with maintaining over 90% power-conversion efficiency. [ABSTRACT FROM AUTHOR]

Recently, several magnetic tunnel junction (MTJ)-based non-volatile ternary content-addressable memory (NV-TCAM) cells have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption during search operations. To address these issues, we propose a novel MTJ-based NV-TCAM cell, which is composed of 15 transistors and 4 MTJs (15T-4MTJ). By utilizing the differential MTJs with complementary states and positive feedback of cross-coupled inverters for sensing, the proposed 15T-4MTJ NV-TCAM cell can significantly improve the search reliability. Moreover, owing to that there is no static current during search operations, only dynamic charging and discharging current, it can achieve ultra-low power consumption. In addition, by using only one transistor as the critical path between the match-line and GND, its switch delay can be shortened, thereby realizing high-speed search operations. Hybrid CMOS/MTJ simulation results of the 144-bit word circuit show that the proposed 15T-4MTJ NV-TCAM cell can obtain a smaller search error rate of 2.7%, a higher search speed of 0.17 ns, and a lower search energy of 0.17 fJ/bit/search in comparison with other MTJ-based NV-TCAM cells. On the other hand, its write energy of 1.589 pJ/bit is about $3.64\times $ smaller than that of the previously proposed 10T-4MTJ NV-TCAM cell. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

Models of inverters and other converters based on averaging have been widely used in numerous simulation applications. Generalized averaging can be applied to model both average and switching behavior of converters while retaining the faster run times associated with average-value models. Herein, generalized average models for single- and three-phase pulse width modulation inverters are proposed. These models are based on a quasi-Fourier series representation of the switching functions that includes fundamental and switching frequency components as well as sideband components of the switching frequency. The proposed models are demonstrated both in simulation and experimentally and are found to accurately portray both the fundamental and the switching behavior of the inverter. In particular, the use of sideband components allows accurate representation of the variation in switching ripple magnitude that occurs in the steady state. The generalized average models are found to have simulation run times that are significantly faster than those associated with detailed models. Therefore, the proposed generalized average models are suitable for simulation applications in which both accuracy (including the switching behavior) and fast run times are required (e.g., long simulation times, systems with multiple converters, and repeated simulations). [ABSTRACT FROM AUTHOR]

In this article, a fully digital system to detect and correct setup/hold time violations in digital circuits, is presented. The proposed system benefits from simple, low-power, small-area, and easy-to-modify design. The system is composed of two separate blocks, detector and corrector connected through a 2-bit control signal. The detector is placed near flip-flops or memory elements and sends control signals to the corrector. Corrector circuitry consists of only CMOS inverters and a multiplexer, either after global clock source to correct clock globally or before the elements to correct them locally. Because of its simplicity, this system can be repeatedly used throughout the chip. Also it is proved that the correction circuitry may be realized by employing only a few CMOS inverters without any need for adjusting the delay of the inverters. Furthermore, mathematical proof for the ability of the inverter-based correction circuitry is provided. The system continuously monitors and corrects any setup/hold time violations up to the highest possible operating frequency a given process allows. [ABSTRACT FROM PUBLISHER]

Increasing the accuracy of circuit delay estimation using Non Linear Delay Model (NLDM) in nanometer range CMOS technologies is highly challenging. To solve this issue, people have started using effective current source model (ECSM) and composite current source model (CCSM), which can both be derived from each other. For a standard cell, ECSM stores certain predefined threshold crossing points (TCPs) of the output voltage waveform with respect to several input transition time (TR) and load capacitance (Cl) values. In this work, we propose an analytical timing model relating all TCPs with Cl and TR values for inverter standard cell. We derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (TR, Cl) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum error of 2.5%. We use this model and the derived relationships with cell size to reduce the number of simulations in ECSM library characterization. Due to process, voltage and on-chip temperature (PVT) variation, re-characterization is done at several PVT corners. In addition, layout dependent effects also lead to an unexpected variation in cell performance. To reduce the characterization effort, we derive relationships of variation of our model coefficients and regions of validity with cell size in mechanical stress enabled CMOS technologies, considering cell layout parameters. We also derive relationships of our model's coefficients with on-chip supply voltage and temperature variations. We use these relationships in reducing number of HSPICE simulations in ECSM re-characterization significantly. [ABSTRACT FROM PUBLISHER]

A new gate drive circuit to reduce the power loss and switching noise of single-inductor-multiple-output regulators is presented. Efficiency degradation and switching noise induced by the cross-talk of the voltages and currents within the power stage and buffer are analyzed. A shoot-through-current (STC) controlled buffer with four-transistor (4T) inverters is presented, and the 4T inverter enables internal STC control and generates two outputs with dead-time. To further isolate the cross-talk, two separate high voltage selectors (HVS) with the proposed buffer are used to power the buffer and the power P-MOSFET body, respectively. Simulation results show that the peak and average currents of the proposed buffer are smaller and much less sensitive to the buffer size than those of the traditional inverter based buffer. Two single-inductor-dual-output boost converters with and without the proposed techniques have been fabricated in a 0.35-\mum CMOS process. Experimental results show that the maximum efficiency is increased from 87.8% to 91.6% with the proposed technique. [ABSTRACT FROM PUBLISHER]

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and, the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 μm CMOS process with the active area of 0.32 mm2. The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 Ps and 86.7 PS, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW. [ABSTRACT FROM AUTHOR]

A generalized study of the parallel connection of N Class-D parallel resonant (LCp) inverters is presented. Steady-state analysis and design considerations are provided in detail, evaluating the current distribution, output power and efficiency of the circuit as a function of the number, N, of phases. Inductor equivalent series resistance and MOSFET conduction losses are considered in order to foresee and optimize the inverter efficiency. The power supplied to the load can be controlled at constant switching frequency by using the phase displacement of the output voltages of each Class-D leg, although for the interests of this specific application, only one inverter is phase shifted. The applicability of the general analysis is demonstrated on two practical designs with three and five phases, resulting in 400-W and 1-kW high-pressure sodium lamp ballasts, respectively. [ABSTRACT FROM AUTHOR]

This study addresses a grid-connected photovoltaic (PV) generation system. In order to make the PV generation system more flexible and expandable, the backstage power circuit is composed of a high step-up converter and a pulsewidth-modulation (PWM) inverter. In the dc-dc power conversion, the high step-up converter is introduced to improve the conversion efficiency of conventional boost converters and to allow the parallel operation of low-voltage PV modules. Moreover, an adaptive total sliding-mode control system is designed for the current control of the PWM inverter to maintain the output current with a higher power factor and less variation under load changes. In addition, an adaptive step-perturbation method is proposed to achieve the objective of maximum power point tracking, and an active sun tracking scheme without any light sensors is investigated to make PV plates face the sun directly in order to capture maximum irradiation and enhance system efficiency. Experimental results are given to verify the validity of the high step-up converter, the PWM inverter control, the ASP method, and the active sun tracker for a grid-connected PV generation system. [ABSTRACT FROM AUTHOR]

Two structures, a switched-capacitor (SC)-based boost converter and a two-level inverter, are connected in cascade. The de multilevel voltage of the first stage becomes the input voltage of the classical inverter, resulting in a staircase waveform for the inverter output voltage. Such a multilevel waveform is close to a sinusoid; its harmonics content can be reduced by multiplying the stage number of the SC converter. The output low-pass filter, customary after a two-level inverter, becomes obsolete, resulting in a small size of the system, as the SC circuit can be miniaturized. Both stages are operated at a high switching frequency, resulting in a high-frequency inverter output, as required by some industrial applications. A Fourier analysis of the output waveform is performed. The design is optimized with reference to the nominal duty-cycle for obtaining the minimum total harmonic distortion. Simulations and experiments on two prototypes, one with a five-level output and one with a seven-level output, confirm the theoretical analysis. [ABSTRACT FROM AUTHOR]

We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-μm and a 0.35-μm process technologies show significant improvements over previous models. [ABSTRACT FROM AUTHOR]