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This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the $\text{V}_{\mathrm {OUT}}$ error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- $\mu \text{V}$ /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns. [ABSTRACT FROM AUTHOR]

The DC-DC converter severs as one of the crucial components in DC microgrid applications. In this paper, a novel low frequency current-mode control strategy is proposed to improve overshoot suppression performance for the boost converter against load current and source voltage disturbances. The control strategy is presented as a cascade dual-loop structure composed of a dynamic current-loop controller with asymmetric saturation and a PI form voltage-loop controller. With the low frequency information of disturbances, the designed dynamic current-loop controller delivers not only promising disturbance suppression but also superior reference current tracking. Simulation and experiment results are provided to illustrate the superiority of the proposed strategy on overshoot suppression. [ABSTRACT FROM AUTHOR]

Most memristor-based associative memory neural networks are focused on classical conditioning and ignored operant conditioning. In this paper, a memristor-based neural network of operant conditioning accorded with biological feature is designed. The designed circuit includes a voltage control module, an operant module and synapse modules. It realizes learning, forgetting, long-term memory, reinforcement and punishment functions based on variable synapse structure and double self-protection measure. Meanwhile, the four factors that affect operant conditioning such as contingency, immediacy, magnitude and deprivation are discussed and implemented. The simulation results in PSPICE show that the circuit can be used to simulate actual conditioned reflex and complicated applications. The memristor-based neural network circuit of operant conditioning provides more references for further development of neural networks. [ABSTRACT FROM AUTHOR]

Eight-switch three-phase post-fault inverter (ESTPI) is widely used as the reconfigured topology of three-phase three-level neutral point clamped DC/AC inverter when open-circuit fault occurs. A key technical challenge for the ESTPI is the post-fault controller design. The existing post-fault control approaches for the ESTPI suffer from the difficulty in trading off the current tracking performance, neutral point voltage (NPV) balancing and common mode voltage (CMV) levels. To solve this problem, this paper proposes an improved predictive current control algorithm. The proposed algorithm contributes to achieve accurate output current tracking while greatly reducing the CMV with a balanced NPV. Simulation and experimental results are presented to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

A novel switching-linear hybrid dynamic regulator architecture with dual-supply low dropout regulators (LDOs) is presented in this paper. This architecture leverages the intrinsic dual supplies to extend the operating range of the LDOs. Furthermore, it increases the thermo-optic tuning efficiency by reducing the LDO dropout voltage through dynamic supply modulation. This architecture is suitable for large-scale thermo-optic tuning in silicon photonics. The efficiency improvement is particularly effective when tracking signals of several adjacent channels are close to each other, e.g., wavelength tuning of a microring array. The principle of this architecture is general and can be implemented using different switching converters and LDOs. A specific design with extensive post-layout simulation results is used to verify the effectiveness of our architecture. Implemented in a 130 nm CMOS process, this design can simultaneously regulate eight output channels with an output swing of 0.8 $\text V_{\text {pp}}$. Its peak efficiency when driving 100 $\Omega $ loads is 92% at 1 V output, and the dynamic efficiency is around 86% when tracking 50 kHz sinusoidal signals. To the best of our knowledge, this is the first time that dynamic supply modulation has been applied to multi-channel thermo-optic tuning of silicon photonic devices. [ABSTRACT FROM AUTHOR]

Primary-side regulation (PSR) flyback topology with discontinuous conduction modulation (DCM) mode has been widely used in low-power application due to its high stability, wide input voltage range, low cost, and low standby power. To improve the output power, continuous conduction modulation (CCM) mode is always introduced. However, in CCM mode, conventional PSR voltage-sampling method cannot realize high precision of output voltage or the voltage sampling method requires complex control of high cost. In this paper, a simple digital voltage sampling scheme with two reference voltages outputted from a digital-to-analog converter (DAC) is put forward to trace the “accurate-point” voltage for DCM and CCM modes. In CCM mode, the sampling voltage error of the “knee-point” voltage can be compensated just by inserting DCM switching cycle to obtain the “accurate-point” voltage. Voltage difference between DCM mode and CCM mode will be eliminated, and high precision is easily realized. The proposed method is verified in a 20V, 65W PSR flyback converter. The sampling method only requires a low speed DAC, three comparators and a digital controller. The output voltage precision is within 0.6% with universal input voltage. [ABSTRACT FROM AUTHOR]

The device faults commonly exist in microgrids (MGs) and often undermine the system stability. However, the existing distributed methods generally design control protocols based on the absence of faults or only considering actuator faults, which limits the applicability of controllers in MG systems. Therefore, this paper investigates an adaptive prescribed fixed-time performance (PFTP) consensus fault-tolerant control (FTC) problem for the voltage regulation of a nonlinear islanded MG inverter-based distributed generators (DGs) with output contactor and actuator fault via the state event-triggered mechanism. The PFTP method for the voltage restoration synchronization error is proposed by constructing a novel performance function to increase the speed of voltage recovery. Based on the estimation properties of fuzzy logic system, an unknown nonlinear function and the residual term of output contactor are estimated. Then, an adaptive state event-triggering mechanism is designed to reduce the communication burden, and its main advantage is that the control protocol is updated in the aperiodic way at the triggering instants. Further, according to backstepping technology, a novel adaptive event-triggered consensus FTC protocol is constructed to achieve the voltage regulation of islanded MG, and a parameter adaptive law is designed to compensate the adverse effects of the output contactor fault. Based on the Lyapunov stability theory, it is proved that the voltage recovery synchronization error satisfies the PFTP, and all signals in the closed-loop systems are cooperatively uniformly ultimately bounded. Finally, the proposed control strategy is also validated by using the MATLAB. [ABSTRACT FROM AUTHOR]

This paper proposes a distributed cooperative control strategy for cyber-physical microgrids in a distributed sparse network with communication delays by using predictive control theory, which enables each distributed generator (DG) unit to achieve voltage restoration. In the proposed control strategy, we first design a primary droop-free model predictive controller to make the output voltage track its nominal set points timely, with the neighbor-based error information a secondary distributed coordinated predictive controller is then proposed to actively compensate the general communication delays for cyber-physical microgrids caused by low-bandwidth communication networks. Sufficient conditions, in terms of communication network connectivity and control gains for the system stability are derived by using the tools of special matrix theory and algebraic graph theory. The proposed control protocols are fully distributed and can be implemented through a sparse communication network and thus, satisfy the plug-and-play feature of the future smart grid. The effectiveness of the control strategy in compensating communication delays is also verified by real-time simulation experiments in OPAL-RT on a test microgrid. [ABSTRACT FROM AUTHOR]

This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to $4.63\times $ lower minimum power consumption and slightly better FoM values than CSROs. [ABSTRACT FROM AUTHOR]

This paper introduces the utilization of two different input-referred offset voltage correction methods applied to multiple amplifiers within a front-end sensing circuit of a buck regulator for the first time. The multi-amplifier system under investigation contains an instrumentation amplifier consisting of three folded cascode stages and an additional amplifier configured as a unity-gain buffer for a reference voltage. The first method in this work alleviates voltage offsets in this 4-amplifier system based on a shared auxiliary amplifier correction circuit that switches between different target amplifiers; whereas the second method applies a chopping-based auto-zero procedure to cancel the input-referred offset voltage of the same amplifiers. Since the instrumentation amplifier is designed for feedback sensing in integrated power management applications, it has a relatively high bandwidth requirement. For this reason, the chopping technique does not involve a low-pass or band-pass filter. Instead, a successive approximation register (SAR) analog-to-digital converter is used to sense the output. Measurements of the amplifiers fabricated in a 130nm CMOS technology demonstrate that the auxiliary auto-zero offset cancellation method leads to lower input-referred offset voltage standard deviation ($\sigma = 1.31\,\,\mu \text{V}$) compared to the chopping technique ($\sigma = 184.67\,\,\mu \text{V}$), and that the die area requirement and power consumption with the auxiliary amplifier-based offset cancellation (0.105 mm2, 1.32 mW) are lower than with the chopping method (0.25 mm2, 1.72 mW). [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

To improve the voltage and power sharing of distributed generations, the hierarchical controls are widely used in microgrids while the dependent communication network makes it difficult to ensure the performance under limited bandwidth. In this paper, a predictive voltage hierarchical controller is designed. With the delayed secondary PI compensation signals, an inner-loop robust control is designed in the primary controller, ensuring stable voltage tracking. Then, a predictive controller is designed to provide neighbor and local predictions, such that the data integrity is improved by an accurate predictive compensation under bidirectional data-loss. Final case study results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper introduces an accurate frequency regulation method based on a constant on-time (COT) buck regulator designed for point-of-load (POL) regulation with a fast load transient requirement and wide load range. Traditional COT regulators suffer from frequency shift due to load variations. The proposed frequency adjustment circuit helps the COT control engine to reach its target frequency of operation by adjusting the on-time pulse under varying conditions. This circuit includes a phase detector and a voltage-to-current converter block. The phase error between the target clock signal and the PWM is directly used to adjust the width of the on-time pulse. This will fine-tune the bandwidth of the frequency regulation loop, which can help to improve the transient performance of the COT as well. The fabricated chip has been tested under 20A/ $\mu \text{s}$ load transient speed with a 10A load step condition. The measured silicon performance shows that the error of the switching frequency is less than 0.16% in the 400kHz to 1MHz range during steady-state operation. [ABSTRACT FROM AUTHOR]

In this paper, a high-order nonlinear disturbance observer-based fractional-order sliding mode control (FOSMC) strategy is proposed for DC/DC buck converters in the presence of mismatched disturbances, ensuring the properties of both stability and dynamic performance. Traditional sliding mode control can deal with matched disturbances while achieving desired closed-loop performance, unfortunately it is particularly sensitive to mismatched disturbances. In the proposed control structure, two nonlinear disturbance observers are constructed to estimate both matched and mismatched disturbances in finite time. Then, the estimated variables are used for the fractional-order sliding mode surface design, where a super twisting sliding mode controller is designed to drive the states of the system to track their desired values. Comparing with the traditional SMC, the proposed method not only reduces the sensitivity of the system to mismatched disturbance, but also improves the transient performance of the system. Simulation and experimental results have comprehensively illustrated the feasibility and effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50-Ω load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50-Ω load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50-Ω load connection. [ABSTRACT FROM AUTHOR]

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of −63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of −241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO’s phase noise (PN), leading to an in-band PN of −116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2. [ABSTRACT FROM AUTHOR]

In this paper, a wideband vector-sum phase shifter with phase linearity enhancement technology is proposed to minimize phase error. The digital phase shifter synthesizes the output phases by modulating and summing four quadrature signals. A common-source stage with transformer-based matching network and a quadrature-all-pass filter (QAF) are utilized for the quadrature signals generation within a wideband. Besides, to decrease the influence of parasitics on amplitude and phase error, a resistor-based compensation technology is employed in the QAF implementation. Then, to obtain the 360° range high resolution phase shifts, the quadrature signals are modulated by four Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current-digital to analog converters (current-DACs). To further minimize phase error, an on-chip phase linearity enhancement loop is utilized. The drain voltages of current-DACs are detected and compared to the presupposed reference voltages generated by the loop. Besides, the compared results are fed back to control the current-DACs to achieve phase linearity enhancement. To verify the mentioned mechanism, a 7-bit digital phase shifter operating at 22–44 GHz with on-chip phase linearity enhancement technology is implemented and fabricated in a 28-nm CMOS technology. Based on the phase linearity enhancement technology, the phase shifter exhibits a RMS amplitude error of 0.36–0.59 dB and RMS phase error of 0.92° −1.02° without off-chip digital pre-distortion (DPD) technology. The total DC power consumption including the phase linearity enhancement loops is 35 mW under a 0.9V supply voltage. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

Disturbances, uncertainties, noises and device faults commonly exist in microgrids and often undermine the system stability. To meet these challenges, robust control methods have been recently employed in microgrids systems. In this paper, an active fault-tolerant control scheme is proposed for DC islanded microgrids subjected to sensor fault and external disturbance. Firstly, a distributed ${H_\infty }$ observer is designed to estimate the uncorrupted voltage and current with high accuracy. Then, an observer based state feedback controller is proposed to ensure stability of voltage regulation for the system. A consensus based control layer in the secondary level is provided to realize current sharing. For the plug-and-play operation of DC microgrids, decentralized parameters design approaches for the observer and controller are both discussed. Finally, simulation studies and experiments are carried out on a DC microgrid system to evaluate the effectiveness of the proposed fault-tolerant control scheme. The simulation and experiment results show that compared with previous works, the proposed observer based control strategy can significantly improve the reliability and resilience of DC microgrid systems. [ABSTRACT FROM AUTHOR]

Because of the different working principles between conventional flyback and active-clamped flyback (ACF), the existing primary-side regulation (PSR) technology cannot be applied to ACF. And in order to achieve PSR of ACF, a low-cost digital sampling method based on the auxiliary winding of the transformer is proposed. In the conventional peak current mode (PCM) controlled ACF, the sampling resistor of primary current may introduce additional power loss, and high-frequency oscillations during sampling may reduce system’s stability. Therefore, a digital feedback-feedforward control (FFC) method is proposed to eliminate the sampling resistor. The stability of the proposed control method and its influence on the dynamic response are studied. In addition, since GaN device has higher power loss during reverse conduction than its Si counterpart, design considerations of reverse conduction time of power switches are also discussed in this paper. All control methods and design considerations are verified on a GaN-based 12V-3A ACF, and the proposed control strategy is implemented by FPGA. [ABSTRACT FROM AUTHOR]

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper proposes a distributed hierarchical control framework for energy storage systems (ESSs) in DC microgrid clusters, which achieves voltage regulation and current sharing for ESSs in each microgrid as well as the whole microgrid cluster. The primary control stage adopts a droop controller which only requires local information while the secondary control stage provides correction terms for ESSs within microgrids. The tertiary control stage samples the pinned ESSs in different microgrids with low sampling rate to provide the voltage setpoint, which ensures global current sharing among microgrid cluster. The corresponding multilayered event-triggered consensus algorithm for clusters is proposed to reduce the communication cost generated by operation of the distributed controller. Both the control framework and the consensus algorithm can be extended for satisfying higher dimensional regulation needs. The controller is validated in a DC microgrid cluster through simulation under different scenarios, and the results illustrate the effectiveness of the proposed controller. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]

Convolution is one of the key operations in signal processing and machine learning applications. In this paper, we propose a novel convolution computing paradigm based on the NOR Flash array (NFA) that is capable of executing the 2-D convolution computing in one clock cycle. In order to demonstrate the feasibility and efficiency of the proposed convolution computing paradigm, the feature extraction task on an image with the size of $20\times 20$ is executed using the NFA structure. We also prove the NOR Flash-driven convolution computing is capable of processing the image with a larger size. This paper presents a new approach to realize convolution computing with high speed and energy efficiency for the signal processing and convolution neural network. [ABSTRACT FROM AUTHOR]

In this paper, four control strategies for DC-DC buck converters are proposed, compared and analyzed: a single-loop adaptive control strategy (SA), a double-loop adaptive control strategy (DA), a single-loop disturbance observer-based control strategy (SDOB) and a double-loop disturbance observer-based control strategy (DDOB). First, the nominal system without considering the parametric uncertainties of the DC-DC buck converter is built to help develop the SA and DA. The SA is built by adaptive and backstepping control approaches, and the DA is set up by adaptive and sliding mode control approaches. Additionally, a model considering parametric uncertainties is introduced, giving the opportunity to develop the SDOB and DDOB. The SDOB is developed using a designed disturbance observer and backstepping control technique, and the DDOB is synthesized using a designed disturbance observer and sliding mode control method. Finally, the advantages and disadvantages of the four proposed control strategies are compared and analyzed through experiments. [ABSTRACT FROM AUTHOR]

A novel class-D flipped voltage follower (FVF) low-dropout (LDO) regulator is proposed and implemented in this paper to supply high load current with fast transient response for sharp load changes. The proposed class-D control generates a multi-level pulse width modulated (MLPWM) signal to the gate of the control transistor that corresponds to the load level. The MLPWM control signal enables wide loop bandwidth and reduces output ripple. The FVF architecture reduces the output impedance and improves the controller efficiency. A novel feed-forward transition-detection path (FFTDP) controls the gate of the power transistor and allows enhanced switching at high loads. The proposed LDO operates with a wide range of input voltages from 1.2V to 1.8V and dropout of 200mV down to 50mV. The implementation responds to load changes from 0-300mA in 7ns with no observed overshoot/undershoot. The output ripple for the LDO is < 7mV with roughly 2.5mV due to ESR resistance. The LDO achieves FOM $_{\mathbf {V}}=1$ mV with a current efficiency of 99.93% at maximum load current. The prototype chip is fabricated on 28-nm CMOS technology and the controller occupies 0.004mm2. [ABSTRACT FROM AUTHOR]

In this paper, an enhanced optimal control technique based on adaptive Maximize-M Kalman filter (AM-MKF) is used. To maximize power extraction from solar PV (Photovoltaic) panel, a learning-based hill climbing (L-HC) algorithm is implemented for a grid integrated solar PV system. For the testing, a three-phase system configuration based on 2-stage topology, and the deployed load on a common connection point (CCP) are considered. The L-HC MPPT algorithm is the modified version of HC (Hill Climbing) algorithm, where issues like, oscillation in steady-state condition and, slow response during dynamic change condition are mitigated. The AM-MKF is an advanced version of KF (Kalman Filter), where for optimal estimation in KF, an AM-M (Adaptive Maximize-M) concept is integrated. The key objective of the novel control strategy is to extract maximum power from the solar panel and to meet the demand of the load. After satisfying the load demand, the rest power is transferred to the grid. However, in the nighttime, the system is used for reactive power support, which mode of operation is known as a DSTATCOM (Distribution Static Compensator). The capability of developed control strategies, is proven through testing on a prototype. During experimentation, different adverse grid conditions, unbalanced load situation and variable solar insolation are considered. In these situations, the satisfactory performances of control techniques prove the effectiveness of the developed control strategy. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

In this paper, we propose a fully-integrated reconfigurable charge pump in a 0.18- $\mu \text{m}$ CMOS process; this converter is applicable for self-powered Internet-of-Things applications. The proposed charge pump uses a two-dimensional frequency modulation technique, which combines both the pulse-frequency modulation (PFM) and pulse-skip modulation (PSM) techniques. The PFM technique adjusts the operating frequency of the converter according to the variations in the load current, and the PSM technique regulates the output voltage. The proposed two-dimensional frequency modulation technique can improve the overall power conversion efficiency and the response time of the converter under light load conditions. A photovoltaic cell was chosen as the input source of the proposed converter. To adapt to the variations in the output voltage of a photovoltaic cell under different light illumination intensities, we built a reconfigurable converter core with multiple power conversion ratios of 2, 2.5, and 3 for the regulated output voltage of 1.2 V when the input voltage ranged from 0.53 V to 0.7 V. Our measurement results prove that the proposed capacitive power converter could achieve a peak power conversion efficiency of 80.8%, and the efficiency was more than 70% for the load current that ranged from $10~\mu \text{A}$ to $620~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

This paper proposes a low power area-efficient multi-mode voltage clamper circuit called pseudo differential pair and applies it into an error amplifier (EA) which can be used in DC-DC converters as a practical design example. In addition to a normal amplifying mode, the error amplifier has two extra operation modes with the help of the voltage clamper, which can limit the maximum output voltage and the maximum sink current, respectively. By inserting this pseudo differential pair of only three transistors in the intermediate stage of the amplifier, a voltage-current feedback is introduced to achieve the voltage limiting function without bringing resistive load to the output stage or unwanted effects to the input stage. The frequency compensation of the EA is also reused in the voltage limiting loop to make the whole block more compact. The circuit is implemented in a $0.35~\mu \text{m}$ BCD process. The verification results match the theoretical analysis very well, which proves that the proposed voltage clamper can effectively enhance transient response of the converter control loop and improve system reliability. Only additional 0.001689 mm2 active area is occupied for about 2X transient speed improvement with fair open loop amplifying performance. [ABSTRACT FROM AUTHOR]

This paper presents an NMOS digital low-dropout regulator (LDO) with fast transient response and ultra-low quiescent current, to provide a tunable power supply for near-threshold voltage computing circuits in internet-of-things (IoT) devices. An LDO with an NMOS power transistor can enjoy the intrinsic fast transient response of the source-follower-like power stage, contributing to the proportional (P) part of the control loop. A shift-register-based digital control serves as an excellent candidate for the integral (I) part of the control loop. In addition, we propose a NAND-gate-based high-pass analog path (NAP) as the derivative (D) part of the loop, making the whole control scheme a complete PID control, therefore, achieving a fast transient response. We fabricated two versions of the prototype chip, one with a 35 pF on-chip load capacitor and a fast-transient on-chip load, and the other with no load capacitor, in 28-nm CMOS. The proposed NMOS digital LDO with NAP can handle the load transient of 160 mA/ns with 810-nA quiescent current, achieving 117-mV voltage undershoot. With the proposed techniques, we can achieve nearly two orders of better FoM when comparing it to the state-of-the-art works. [ABSTRACT FROM AUTHOR]

This paper introduces a fully integrated switched-capacitor (SC) DC-DC boost converter suitable for energy harvesting in miniature sensor systems with varying harvesting source and battery voltages. Unlike the conventional SC DC-DC boost converters, where efficiency is optimized only for a few topology-dependent voltage conversion ratios (VCRs), the proposed soft-charging-based SC converter achieved VCR-insensitive evenly high efficiency for a wide range of input and output voltages. A test chip was fabricated in 180nm process, and the measured peak efficiency and average efficiency are 85.3% and 83.6%, respectively, for 1.8V regulated output voltage and a wide range of input voltages (0.95–1.8 V). Also, a peak efficiency of 88.9% and average efficiency of 87.6% are achieved for a wide range of battery output voltages (3.0–4.2 V) and a 1.2V harvesting source input voltage. [ABSTRACT FROM AUTHOR]

This paper presents a thermal/RF hybrid energy harvester. The energy harvesting system can scavenge energy from a thermoelectric generator (TEG) and a radio-frequency (RF) energy source simultaneously, and deliver the combined power to a single load. Two techniques are employed in the system to increase the end-to-end efficiency; the rectifying-combination technique is proposed to eliminate the power loss associated with a dedicated AC-DC converter before the combiner and an improved fractional open-circuit voltage (FOCV) maximum power tracking (MPPT) is considered for a high average efficiency. A dynamic power path control extracts the maximum RF power from a cross-coupled differential rectifier, and also behaves as an AC/DC energy combiner. The thermal/RF harvester system achieves a measured peak end-to-end power conversion efficiency (PCE) of 63.4%. The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester. Fabricated in 0.18 $\mu \text{m}$ CMOS technology, the prototype operates at a thermal input voltage ranging from 40 mV to 400 mV and an RF power from −18 dBm to −3 dBm and delivers an output voltage of 1.8 V. The total area of the fabricated circuit prototype is 1.22 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their conversion ratios is also proposed in this work. To verify this method, we demonstrate the design of an example compact MOSCVR. The MOSCVR is capable of simultaneously producing four different output voltages from a single input power supply with only two flying capacitors and twelve switches. The study presented in this work provides not only comprehensive insight but also guidance to find the suitable topology of a compact MOSCVR. [ABSTRACT FROM AUTHOR]

This paper introduces an on-chip distributed power delivery grid (DPDG) with cooperative regulation and IR-drop reduction based on analog-assisted digital LDOs (AADLDOs), which inherit the merits of low output ripple and sub-LSB current supply ability from the analog control, and the advantage of low supply voltage operation and adaptive fast response from the digital control. With the distributed power delivery topology, the IR-drop across the power supply rail can be reduced, especially in large area power-supply applications. The AADLDOs in the power delivery grid work cooperatively to obtain a balance between improved response speed and power consumption. A prototype of a 3 × 3 power grid with 9 AADLDOs, providing a total of 500-mA maximum load current with an on-chip 0.9-nF output capacitor, is fabricated in a 65-nm CMOS process to demonstrate the proposed DPDG concept and the effectiveness of this scheme. A maximum voltage undershoot of 125mV is measured with a 450mA/20ns load step, resulting a figure-of-merit as low as 0.249ps. [ABSTRACT FROM AUTHOR]

This paper presents an IC that extends the voltage capability of a low voltage battery charger to 100V for accurately and reliably charging lithium ion (Li-Ion) battery stacks of up to 18 cells. The IC interfaces with a buck converter battery charger that utilizes external nFET control and an external inductor current sensing resistor. The voltage extender IC provides voltage level translation for the nFET control signals and the current sensing function while supporting an input power supply voltage of up to 100V and output battery voltage of up to 80V. The inductor current sense voltage is translated with a ping-pong amplifier capable of driving a bi-directional input voltage to a fully differential output with a maximum load current of 10 mA at 20 MHz bandwidth and less than $500~\mu \text{V}$ offset. The combined system of the voltage extender IC and battery charger achieved 97% efficiency at a 4-A charging current. The battery charging voltage accuracy was better than ± 0.5% at 80V. [ABSTRACT FROM AUTHOR]

In this paper, a novel adaptive second-order sliding mode (SOSM) control method is proposed by combining a new adaptive strategy with the backstepping-like technique. The new adaptive strategy is first constructed by means of the equivalent control for which a sliding-mode-based filter is employed rather than the widely-used low-pass filter such that the parameter restriction under the usage of low-pass filter can be relaxed. Then, by applying the proposed adaptive strategy and the idea of adding a power integrator, an adaptive SOSM method is established to finite-time stabilize the sliding variables. The feature of the proposed SOSM method lies in that the gain will vary with the size of the lumped uncertainty so as to avoid the overestimation of the gain. The stability analysis is given based on the finite-time Lyapunov theory. The theoretical results are finally applied to the voltage regulation problem of a Buck converter. [ABSTRACT FROM AUTHOR]

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm2 and 0.0126 mm2, respectively. The system also contains an off-the-shelf 3.2 mm $\times2.5$ mm $\times0.9$ mm supercapacitor working as an off-chip battery or energy reservoir between the PMU and the voltage regulator. Experimental results show that the fast energy recovery of the on-chip solar cell and PMU permits the system to replenish the supercapacitor with enough charge as to sustain Bluetooth Low Energy (BLE) communications even with input light powers of 510 nW. The whole system is able to self-start-up without external mechanisms at 340 nW. This work is the first step towards a self-supplied sensor node with processing and communication capabilities. The small form factor and ultra-low power consumption of the system components is in compliance with biomedical applications requirements. [ABSTRACT FROM AUTHOR]

In this paper, we present a battery management technique that significantly increases the battery lifetime of event-based devices that are predominantly in standby mode without requiring off or on chip large power switches. The proposed technique uses a novel battery management technique to remove Wake-Up Receiver (WUR) Low Drop-Out (LDO) unit, while causing minimal change to the system’s power supply configuration. This technique manages the system so that it can wake up to a normal battery configuration while sleeping in a different battery set-up. This, as a result, drops standby power consumption significantly, making the proposed technique suitable for IoT sensors and, in general, event-based devices. Battery management comprises of voltage level detector, switches for changing battery configuration, and voltage level shifters. The design was applied to an active Radio Frequency Identification (RFID) tag with an embedded WUR and fabricated using TSMC 180nm technology. Measurements on the test chip showed that the proposed architecture and design leads to 80% standby energy saving, prolonging overall (active plus standby) battery’s lifetime by 2.5 times while having negligible area overhead. The advantages and disadvantages of the proposed technique are also presented and discussed. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper presents, a wide input range, 4-stage threshold voltage compensated RF-to-DC power converter, designed to efficiently convert RF signals to dc voltages by applying an optimum compensation voltage produced by subthreshold auxiliary transistors. The proposed optimally compensated rectifiers can achieve higher efficiency over a wider input power range compared to other threshold voltage compensation circuits where the level of the compensation is limited by the circuit structure and varies with input power. The designed rectifier is implemented in three possible ways. This proposed compensation technique can be applied to a rectifier chain with a relatively low number of stages. Designed and implemented in a 130 nm CMOS technology, the proposed rectifier exhibits a measured PCE of above 20% over the 8.5-dB input power range while driving a 1- $\text{M}\Omega $ load resistor at 896-MHz. For the same load and utilizing a minimal number of compensated rectifier stages, the proposed circuit exhibits a maximum PCE of 43% at −11 dBm for single-ended Dickson-based CMOS rectifiers. The proposed circuit demonstrates a −20.5 dBm sensitivity for 1 V output across a 1- $\text{M}\Omega $ resistive load. [ABSTRACT FROM AUTHOR]

Voltage source converters (VSCs) have been widely used in modern power systems. Consequently, reliable operations of VSCs are essential for the power system to operate properly. A parameter estimator (PE) for a VSC system acts as a useful tool for problem diagnosis and preventive maintenance. Generally speaking, depending on how the measurement data are attained, a parameter estimation method can be classified into invasive and non-invasive. Non-invasive methods, which do not require any external excitation, are generally preferred for parameter estimation. However, most of the PEs can only estimate some parameters of the converters while treating others constant. This paper proposes a non-invasive parameter estimation method, which is able to predict simultaneously the circuit and control parameters of a VSC. To achieve this, the accurate open-loop and closed-loop steady-state models of the VSC are first derived. These models will be used to generate the training data sets to obtain the artificial neural network models to account for various uncertainties in a practical circuit. All the training data are generated by the derived VSC models, which are constructed in MATLAB and run off-line. The proposed method has been verified via PSCAD/EMTDC and validated with the experiment. [ABSTRACT FROM AUTHOR]

In this paper, we propose two ferroelectric FET (FEFET)-based non-volatile flip-flops (NVFFs). The proposed NVFFs can handle both controlled and automatic per-cycle backup to address sudden power failure. FE layer can be either positively polarized or negatively polarized. Depending on these polarization states, the FE layer can save either “1” or “0.” To depolarize (i.e., negatively polarize) the ferroelectric layer of an n-type FEFET, a negative gate-to-source voltage is needed, which introduces a challenge. We exploit data-dependent source voltage control to achieve both polarization and depolarization. The proposed NVFFs (NVFF-1 and NVFF-2) can store data every cycle, which is necessary for energy-harvesting applications and devices with an unreliable power source. We also present a modified version of NVFF-2 (NVFF-2a) that can backup data in a controlled fashion and facilitate low-voltage normal mode operation. The proposed circuits introduce only three-to-four additional transistors in the design, which offer a lower area-overhead than contemporary standard FEFET-based NVFFs. Moreover, the FEFET-based NVFFs offer low energy (in the order of fJ) and delay (in the order of tens of ps) behavior, which is advantageous in energy-harvesting non-volatile processors. [ABSTRACT FROM AUTHOR]

In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58% when the charger operates in the turbo boost mode, and achieves 97% maximum efficiency when the charger operates in buck charge mode. [ABSTRACT FROM AUTHOR]

For the average current mode (ACM)-controlled boost power factor correction (PFC) converter, there is line frequency instability under light load and small output capacitor conditions. The line frequency instability is characterized as self-oscillation in the form of period-doubling, which drastically increases the total harmonic distortion (THD) and additional losses. Regarding this line frequency instability, this paper proposes a stability control scheme incorporating an outer-voltage proportional controller and an additional third current-harmonic feedforward compensation (TCFC). Specifically, the outer-voltage proportional controller replaces the traditional low-pass filter (LPF) to mitigate the line frequency instability, and the TCFC aims to ensure an acceptable THD. Moreover, the dynamic response of the proposed current-feedforward-based stability control scheme outperforms the existing voltage-feedback-based schemes. Furthermore, the control parameters are determined by the harmonic averaged model, and the feasibility of the proposed scheme is verified by experiments based on IC UC3854BN. The experimental results demonstrate that the THD with the line frequency instability is 56.60%, while it is improved to 15.58% by using the proposed scheme. [ABSTRACT FROM AUTHOR]

The recently-proposed dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is a promising approach for enabling the implementation of multiple fully-integrated power supplies with superior dynamic and cross-regulation performance in SoCs. However, switching the input and output stages at different frequencies raises many questions about the optimum strategy for controlling such converter topology. This paper explores and analyzes the various classes of controllers that can be employed in the output stage of the DF-SIMO buck converter topology, while taking account of key comparison metrics, such as circuit complexity, stability, steady-state and dynamic performance, and the range of operating conditions each controller may be suitable for. This includes average-based voltage-mode, ripple-based charge-mode, and ripple-based voltage-mode controllers. The predictions made by the analytical expressions derived for the various controllers are verified through system-level and transistor-level circuit simulations. [ABSTRACT FROM AUTHOR]