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This paper presents an overview of proximity wireless communication (PWC) technologies, their principles, design guidelines and practical applications. In particular, two different applications of PWC are reviewed. One is PWC between stacked chips. Both communication distance and coupler size are several tens of microns. Area and energy efficient design techniques are introduced. Another is PWC between module boards. Both communication distance and coupler size are several millimeters. Energy and area efficient practical designs are introduced for mobile and industrial machinery applications. [ABSTRACT FROM AUTHOR]

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to $4.63\times $ lower minimum power consumption and slightly better FoM values than CSROs. [ABSTRACT FROM AUTHOR]

Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies. [ABSTRACT FROM AUTHOR]

Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately join in the following message propagating of the current iteration and accelerates the decoding convergence. In this paper, a row-layered message passing algorithm (MPA) is proposed, which offers a good trade-off between the hardware complexity and the bit error rate (BER) performance. Simulation results show that the proposed decoder saves 66.7% computation complexity compared with the original MPA with the similar BER performance. Pipelining and folding technology are adopted in VLSI implementations. The synthesis results with 45-nm CMOS technology show that the proposed decoder can achieve higher hardware efficiency and throughput under a high frequency than the existing decoders, achieving 1777.78 Mb/s throughput with 1.112 mm2 area consumption. [ABSTRACT FROM AUTHOR]

In the transmit signal path of a cellular terminal that supports the Long-Term Evolution (LTE) standard, the third-order counter-intermodulation (CIM3) product can be a significant contributor to spurious emissions in protected bands, primarily in cases where all the transmit power is concentrated in one resource block at the edge of the allocated bandwidth. This problem can be addressed with a harmonic rejection architecture for the up-conversion mixer in the transceiver. Prior work in this area retains the four-phase baseband inputs of a conventional quadrature mixer, utilizes various techniques in the local oscillator (LO) path involving overlapping LO waveforms to suppress harmonics and requires the digitally-controlled oscillator (DCO) to be operated at two or more times the LO frequency. The harmonic rejection architecture presented in this paper has six baseband phases and six non-overlapping LO phases and, for higher-frequency bands, allows the DCO to run at 1.5 times the LO frequency. It also provides an inherently higher uncalibrated image rejection than architectures with quadrature baseband inputs, which is advantageous for any wireless communication standard that supports higher-order quadrature amplitude modulation (QAM) schemes such as 1024-QAM and 4096-QAM. [ABSTRACT FROM AUTHOR]

In this paper, a new effective approach is proposed to design compact multifunctional reconfigurable filtering power divider (FPD) based on a developed tunable multi-mode FPD topology. Different from conventional tunable FPD method by cascading tunable filter with power divider (PD), and double tunable filtering structures based on the tunable FPD method, it provides one promising solution of high operation performance, miniaturization and design flexibility enhancement etc., for industrial multi-functional modern wireless communication systems. By reformulating the traditional coupling matrix in terms of element-variable coupling coefficients for the developed tunable FPD topology, bandwidth (BW), center frequency (CF), as well as power division ratio (PDR) tuning are well accounted, which can help guide a new class of tunable FPD designs. For demonstration, a new second-order tunable FPD with only one common ring loaded coupled line tunable resonant unit is implemented as an example without losing generality. Higher-order tunable FPD case is further discussed and investigated by freely generalizing the FPD structure through the adoption of different tunable resonant units without dramatically increasing circuit complexity and size. Experimental results indicates that an improved performance (wider tuning range for CF, BW and PDR with nice isolation and matching), a very compact size and flexible design are achieved in the proposed work, which stands out from those in the literature. [ABSTRACT FROM AUTHOR]

Emerging wireless communication services require the efficient use of available spectrum and improved co-existence of different standards placed in adjacent frequency bands. Co-existence with leakage from primary users in adjacent channels, which falls in the band of interest, is a primary concern for existing and emerging technologies. In this paper, a mixed signal IC technique based on direct sequence spread spectrum is proposed to improve co-existence of radar systems with commercial wireless communication systems. A sinusoid-like pseudo-random sequence is introduced to reduce leakage from radar systems into adjacent channels. The proposed approach reduces the radar signal leakage on adjacent channels by about 22dB when compared with the conventional binary pseudo-random sequence. The proposed technique randomizes narrow and wideband systematic in-band interference, after which interference power can be effectively attenuated through averaging techniques. Experimental results from a 40nm CMOS technology modulator/demodulator prototype demonstrates the feasibility of the proposed architecture. The modulator and demodulator system requires a silicon area of 0.0459mm2 and consumes 4.33mW in total. [ABSTRACT FROM AUTHOR]

Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we implement and combine advanced compressive sampling algorithms to reduce the power requirements of wireless telemetry. Moreover, we apply variable compression, to dynamically modify the device performance, based on the actual signal need. This paper presents an area-efficient adaptive system for wireless implantable devices, which dynamically reduces the power requirements yielding compression rates from $8{\times}$ to $64{\times }$ , with a high reconstruction performance, as qualitatively demonstrated on a human data set. Two different versions of the encoder have been designed and tested, one with and the second without the adaptive compression, requiring an area of $230{\times }235\,\,\mu \text{m}$ and $200\times 190\,\,\mu \text{m}$ , respectively, while consuming only 0.47 $\mu \text{W}$ at 0.8 V. The system is powered by a 4-coil inductive link with measured power transmission efficiency of 36%, while the distance between the external and internal coils is 10 mm. Wireless data communication is established by an OOK modulated narrowband and an IR-UWB transmitter, while consuming 124.2 pJ/bit and 45.2 pJ/pulse, respectively. [ABSTRACT FROM AUTHOR]

Analog-to-digital and digital-to-analog conversion devices for signals with very large bandwidth are not always available due to technical or cost issues. This limits the realization of very high data-rate digital communication systems. In this paper, we propose a dual pulse shaping (DPS) transmission scheme, which can achieve full Nyquist rate transmission with only a half of the sampling rate for each of the two data streams. Two classes of ideal complementary Nyquist pulses are formulated assuming raised-cosine (RC) pulse shaping. The condition for cross-symbol interference (CSI) free transmission is derived and validated for the proposed pulses. Structures of the DPS transmitter and receiver are described and low-complexity equalization techniques tailored to DPS are proposed. With DPS, a millimeter wave system with commercially available and affordable data conversion devices is exemplified for achieving high-speed low-cost wireless communications. Simulation results with two sets of practical dual spectral shaping pulses are provided. The results verify the effectiveness of the proposed scheme, with comparison to the benchmark conventional Nyquist pulse shaping system. [ABSTRACT FROM AUTHOR]

This paper presents implementation friendly VLSI-algorithms for maximum-eigenvalue-detection (MED), energy with minimum-eigenvalue (EME), and mean-to-square extreme-eigenvalue (MSEE) based blind spectrum sensing algorithms. We propose to use efficient iterative power-method for computing maximum and minimum eigenvalues for these algorithms that complemented our hardware design. New VLSI architectures based on suggested spectrum sensing algorithms have been presented in this work. We present two types of sensor architectures: (1) memory-less & low-latency (2) memory-based & resource-shared spectrum-sensor architectures. Former type targets to achieve lower sensing time with adequate hardware efficiency and the later ones are highly resource shared to consume lesser hardware with moderate sensing time. Performance analyses of suggested MED, MSEE and EME spectrum sensing algorithms in AWGN environment showed that the detection probability of 0.75 could be achieved at the SNRs of −12 dB, −10 dB and −7 dB respectively. On synthesizing and post-layout simulating our sensor architectures in 90 nm-CMOS process with the supply of 1.2 V, they could operate at the maximum clock frequency up to 408 MHz delivering sensing time in the range of $23- 44\,\,\mu \text{s}$. The proposed spectrum sensors have achieved $5.5\times $ and $19\times $ better sensing time and hardware efficiency, respectively, compared to the state-of-the-art implementations. Eventually, the memory-based spectrum sensors are FPGA prototyped and tested, at 100 MHz clock frequency, in DVB-T signal environment with OFDM modulated transmitted signals in 2K size IFFT-mode. [ABSTRACT FROM AUTHOR]

This paper discusses a wideband variable-gain amplifier (VGA) implemented in a 28-nm FDSOI CMOS technology. This VGA employs optimal-biasing and differential large-signal pre-distortion linearizations that operate over all gain settings and over its frequency range. The 0.4-to-4-GHz VGA, which consists of its core circuit and an output buffer, exhibits a wideband gain ranging from 4.6 to 12 dB in 1-dB steps and an input return loss higher than 10 dB while demonstrating a worst-case IM3 of −54 dBm across the gain range at ~0-dBm output power and noise figures from 3 to 5.9 dB at 12 dB gain. The VGA and buffer consume 15 mA and 60 mA from a 1.5 V supply, respectively. The total chip area, including the bond pads, is ${1\times 1\,\text {mm}^{2}}$. [ABSTRACT FROM AUTHOR]

The tunability in phase characteristics becomes more and more important in the modern wireless communication system. However, the existing phase tunable coupler structures suffer from the narrow bandwidth and limited tunable range due to the much more complex design requirements. The further deterioration in performance occurs when additional tunability in operating frequency is considered. In this paper, a new simultaneously phase- and frequency- tunable coupler is proposed with the enhancement in both bandwidth and phase tunable range. Two tunable capacitors are loaded on the two terminals of a coupled line section to realize a novel tunable transmission line. This tunable element is introduced between two quarter-wavelength coupled line sections to implement the simultaneous tunability in both phase and operating frequency. For demonstration purpose, a highly flexible 3 dB coupler was designed, fabricated and measured. For a fixed operating frequency of 2.4 GHz, the coupler can provide a continuously tunable phase difference from 30° to 150° within a 10% bandwidth. For a standard phase difference of 90°, the operating frequency of the same coupler can be varied from 2.0 GHz to 2.75 GHz. Good performance in return loss, isolation, and output amplitude imbalance is achieved for all these states. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-time 4-0 MASH $\Delta \Sigma $ modulator with high power efficiency for wide-bandwidth wireless communication systems. An asynchronous successive-approximation-register (ASAR) is used as the quantizer in the $\Delta \Sigma $ modulator to reduce the power consumption and to cancel the comparator mismatch of the conventional flash quantizer. An on-chip background half-range dithering-based calibration technique is proposed to improve the multi-bit feedback digital-to-analog converter matching, with limited overhead cost in terms of power consumption and area. To alleviate the metastability error of the ASAR and to increase the bandwidth, a zero-order loop is added to further quantize the intrinsic quantization error of the ASAR. The design is fabricated in a 28-nm bulk CMOS process. Clocked at a frequency of 1.7 GHz, the modulator achieves 68.5-dB SNDR and 83.6-dB spurious-free dynamic range over an 85-MHz bandwidth, while consuming 23.9-mW power, leading to an excellent Walden figure-of-merit of 64.9 fJ/step and a Schreier figure-of-merit of 164 dB. [ABSTRACT FROM AUTHOR]

Multi-user multiple-input and multiple-output (MU-MIMO) precoding is an effective transmission scheme for achieving very high spectral efficiency in modern wireless communication systems. Although numerous multi-user precoder designs have been proposed over the last few decades, the signal-to-leakage-and-noise ratio (SLNR)-based precoder is known to achieve favorable performance-complexity tradeoffs. This paper presents a new generalized eigenvalue decomposition (GEVD) processor, that is, the core processing unit dominating the overall complexity in SLNR-based precoders. A low-complexity square-root algorithm is adopted to eliminate the need for matrix multiplications and matrix inversion computations, which reduces the complexity of the GEVD processor considerably. Finally, the proposed processor was designed and implemented by using a 40-nm complementary metal–oxide–semiconductor technology, which exhibited a maximum throughput rate of 1.1-M matrices/s for the MU-MIMO system. [ABSTRACT FROM AUTHOR]

Associative processors, while ideal for vector-based applications, have been limited in their use mainly due to area and energy considerations. This reality is changing due to the advent of ultra-dense resistive memories (RRAMs), allowing for area efficient implementations of in-memory associative processors. However, with the high levels of integration, issues related to power density become the major bottleneck. In this paper, we investigate approximate computing in RRAM-based associative processors as a means of enhancing energy efficiency for in-memory associative processors. A case study of a wireless communication system is considered, where fast Fourier transform (FFT) modules are widely used. The proposed manager adjusts the bit width based on the channel SNR, aiming at achieving the desired performance at a reduced energy consumption. An analytical model of system performance under the reduced bit width induced noise is presented. Based on this model, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves the desired performance goals. Simulation results show that the proposed algorithm can achieve up to 45% energy savings as compared to wireless communication systems using conventional RRAM FFT associative processor. [ABSTRACT FROM AUTHOR]

Polar codes have received increasing attention in the past decade, and have been selected for the next generation of the wireless communication standard. Most research on polar codes has focused on codes constructed from a $2\times 2$ polarization matrix, called binary kernel: codes constructed from binary kernels have code lengths that are bound to powers of 2. A few recent works have proposed construction methods based on multiple kernels of different dimensions, not only binary ones, allowing code lengths different from powers of 2. In this paper, we design and implement the first multi-kernel successive cancellation polar code decoder in literature. It can decode any code constructed with binary and ternary kernels: the architecture, sized for a maximum code length $N_{\max }$ , is fully flexible in terms of code length, code rate, and kernel sequence. The decoder can achieve a frequency of over 1 GHz in 65 nm CMOS technology, and a throughput of 615 Mb/s. The area occupation ranges between 0.11 mm2 for $N_{\max }=256$ and 2.01 mm2 for $N_{\max }=4096$. Implementation results show an unprecedented degree of flexibility: with $N_{\max }=4096$ , up to 55 code lengths can be decoded with the same hardware, along with any kernel sequence and code rate. [ABSTRACT FROM AUTHOR]

Millimeter-wave (mm-Wave) communication, operating from 30- to 300-GHz bands with wider available spectrum, has now emerged as a promising solution for future wireless systems. To reduce the hardware complexity of mm-Wave transceivers, beam-selection techniques combined with beamspace multiple-input multiple-output (MIMO) communications have been proposed in the literature. In such a system, beam selection is performed to exploit the near-sparse nature in the mm-Wave channel and, hence, is crucial to the system performance. This paper presents the world’s first digital signal processing (DSP) architecture design for beam selection operation in an mm-Wave multi-user MIMO system. A computationally efficient beam-selection algorithm is first presented. Based on the proposed algorithm, a hardware-scalable beam selection processor is implemented using coordinate rotation digital computers arithmetic. To establish the validity of the concept, the proposed processor is implemented in a 40-nm CMOS technology, integrating 360k logic gates in an area of 0.5625 mm2, while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users. [ABSTRACT FROM AUTHOR]

This paper presents an energy-efficient network-on-chip (NoC)-based multi-core architecture for realizing a reconfigurable Viterbi decoder (VD). The proposed architecture can support a wide range of wireless communication standards that have varied constraint lengths. The energy efficiency in the proposed architecture has been primarily achieved by mapping the add–compare–select operations of the VD onto a $4\times 4$ ZMesh topology-based NoC and then by employing a reconfigurable memoryless survivor memory unit to decode the input symbols. When compared with the existing ASIC-based multi-core VD architectures, the proposed architecture achieves an improvement by at least 3.06 times in the energy consumption per decoded bit (EC) metric. Similarly, when compared with the state-of-the-art single-core VD architectures, the proposed architecture achieves an improvement by at least 4.99 times in the EC metric. [ABSTRACT FROM AUTHOR]

This paper presents a $W$ -band (92–100 GHz) phased array receive channel adopting a power domain vector modulator (VM), which utilizes a 90° hybrid-coupler-based phase interpolator. The quadrature hybrid leverages its inherent functions of quadrature phase splitting and power combining to interpolate phases by combining the weighted signals from variable gain amplifiers in the power domain. Compared with prior active VMs, in the proposed VM, the phases are synthesized in a pure passive network with a matched impedance, less vulnerable to circuit nonlinearity. The distributed 90°-hybrid coupler offers a wideband operation of quadrature phasing and phase interpolation, resulting in a low phase error over the $W$ -band. The measured VM peak-to-peak gain variation for all 5-bit phase states is 7.7–11 dB at the expense of 31-mW dc power from 2.2-V supply voltage. The measured rms gain error is <1.6 dB over 93–108 GHz and the rms phase error is <1.5° at 94 GHz. The output $P_{-1\,{\mathrm{ dB}}}$ is −4 dBm at 94 GHz at the highest gain state. In the receive channel employing the 90°-hybrid-based VM, the peak-to-peak gain variation is 23–26 dB with 9.3–11-dB NF at the expense of 50-mW dc power from 2.2-V supply voltage. The measured input $P_{-1\,{\mathrm{ dB}}}$ is −26 dBm. The chip size of the receive channel, implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process, is $1.65\times0.55$ mm $^{\vphantom {R^{l}}2}$. [ABSTRACT FROM AUTHOR]

This paper presents an analysis based on the impulse sensitivity function to precisely characterize and estimate the jitter caused by the common-mode interference (CMI). Unlike the conventional common-mode rejection ratio concept, the proposed method considers the CMI jitter in a transient rather than in an ac perspective. Inspired by the analytical results, we propose a clock receiver circuit (CRC) based on the self-bias amplifier topology. The accuracy of the analysis and the efficiency of the proposed CRC are verified both in simulations and measurements. A 1-GS/s ADC was fabricated in 65-nm CMOS containing simultaneously three CRCs, including an inverter-chain, a differential amplifier and the proposed structure, serving as the sampling clock. Both simulation and measurement results show a good agreement with the presented analysis. The proposed CRC achieves a 30-fsms jitter with a 620- \mu \textW power at 1.2 V supply. With a similar CMI rejection and random jitter performance, the proposed CRC exhibits a 20-fold power reduction when compared with the state-of-art designs. [ABSTRACT FROM PUBLISHER]

Compressed sensing (CS) analog to information converters (AICs) offer key benefits for signal reception or detection when the input signal is sparse. So far AICs have been demonstrated in environments with controlled input signal conditions and with fixed sparsity levels. This paper investigates how to make AICs effectively operate in dynamic environments with changing signal conditions and thus changing sparsity levels. We focus on RF spectrum scanning, where signals or interferers need to be detected across a wide dynamic RF spectrum, but the presented concepts are widely applicable for low-pass and band-pass CS AICs. The number of measurements and hence the number of branches required in a CS RF front end scales with the sparsity level, i.e. the number of signals that need to be detected. In practice this leads to excessively large silicon area for more than a few signals (e.g., six). We introduce the time-segmented quadrature analog-to-information converter (TS-QAIC), a scalable architecture for signal detection in dynamically changing spectrum environments. While our TS-QAIC prototype implements a fixed number of hardware branches, we experimentally demonstrate adaptive thresholding and adaptive time segmentation to adjust its signal detection capability to the sparsity level of the input signal. [ABSTRACT FROM PUBLISHER]

This paper presents the system architecture, modeling, and design constraints of a wireless chip-to-chip-communication transceiver as a low-power alternative to wireline links, such as PCI-Express. On top of the potential power savings, the wireless link provides lower latency times, better flexibility, lower complexity, and easier heat diffusion. The proposed transceiver uses impulse-radio ultra-wideband communication at 10 GHz. It supports a 2.5-Gb/s data rate with pulse position modulation over short distances (~10 cm). The hardware complexity is reduced by using a modified non-coherent receiver with a rectifying RF front-end and a relative-compare analog baseband. The system performance is quantified and tradeoffs are explored with the main motivation of reducing power. A discussion of the modulation choice, the performance specifications of the receiver blocks and the clock generation principle is presented. We show that energy efficiency better than 6 pJ/bit could be reached with the proposed architecture. [ABSTRACT FROM PUBLISHER]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

Channel estimation errors have a critical impact on the reliability of wireless communication systems. While virtually all existing wireless receivers separate channel estimation from data detection, it is well known that joint channel estimation and data detection (JED) significantly outperforms conventional methods at the cost of high computational complexity. In this paper, we propose a novel JED algorithm and corresponding VLSI designs for large single-input multiple-output (SIMO) wireless systems that use constant-modulus constellations. The proposed algorithm is referred to as PRojection Onto conveX hull (PrOX) and relies on biconvex relaxation (BCR), which enables us to efficiently compute an approximate solution of the maximum-likelihood JED problem. Since BCR solves a biconvex problem via alternating optimization, we provide a theoretical convergence analysis for PrOX. We design a scalable, high-throughput VLSI architecture that uses a linear array of processing elements to minimize hardware complexity. We develop corresponding field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs, and we demonstrate that PrOX significantly outperforms the only other existing JED design in terms of throughput, hardware-efficiency, and energy-efficiency. [ABSTRACT FROM AUTHOR]

Sparse code multiple access (SCMA) is a promising multiple access technology candidate for the next-generation communication system, which can dramatically improve spectral efficiency. However, the major challenge of SCMA is the very high detection complexity. Stochastic computing is a new number representation, which can carry out complex computations with very simple logics. In this paper, we extend the application of stochastic computing to SCMA detection and propose a low complexity stochastic SCMA detector. We also design three novel stochastic logic architectures: a new low hardware cost bit stream generation architecture, a low hardware cost stochastic function node update architecture and a fast converging stochastic variable node update architecture. Analysis and simulation results show that the proposed stochastic SCMA detector saves 69% complexity compared with the traditional SCMA detectors with a comparable bit error rate performance. The synthesis results with SIMC 65-nm CMOS technology show that the proposed stochastic SCMA detector achieves 640 Mbps total system throughput with only 1.45-mm $^{{{2}}}$ cell area. [ABSTRACT FROM PUBLISHER]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

This paper presents a complex delta–sigma modulator (CDSM) designed for integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20–30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. [ABSTRACT FROM PUBLISHER]

Bivariate function approximation has proven its feasibility in terms of hardware-efficient arithmetic signal processing. However, its impact on high performance QR decomposition (QRD) has only been roughly studied so far. In this paper, a novel hardware architecture for Givens-Rotation-based QRD is proposed targeting hardware efficient signal processing. To this end, an ingenious triangular systolic array structure is considered. Complex-valued matrices are efficiently processed by means of a sophisticated bivariate numeric function approximation methodology. In order to get a comprehensive insight in the performance, exhaustive evaluation is carried out with a modern multi-antenna wireless communication system. In detail, the proposed QRD hardware architecture is used in a suitable channel pre-coding setup. For a meaningful proof-of-concept, our work is evaluated on several levels of the computing stack. In addition, our design is implemented and physically synthesized in a state-of-the-art 65-nm Taiwan Semiconductor Manufacturing Company technology and compared with other publications. The results indicate our approach to be a powerful solution for hardware-based QRD, especially in terms of energy and area requirements. [ABSTRACT FROM AUTHOR]

The Internet of Things communicates with the world by using a wide range of different sensors and actuators. These interfaces are based on a wide range of various protocols, such as I2C, SPI, RS232, 1-wire, and so on. There are two conceptional different solutions to provide these interfaces. One is to use dedicated hardware for it. An example would be to use a peripheral on a system-on-a-chip (SoC). All SoC providers offer the families of SoC solutions with different kind of hardware peripheral combinations. The alternative concept it to run virtual peripherals as a software routine on a CPU, preferable on a multithreaded CPU. C-Slow Retiming (CSR) is a known design transformation to generate multithreaded CPUs. This paper argues, that system hyper pipelining overcomes the limitations of CSR by adding thread stalling, bypassing, and reordering techniques to better cope with the challenges of multithreading. This dynamic multithreaded environment is ideal for running virtual peripheral. The benefits of using system hyper pipelining for virtual peripherals are demonstrated on a Cortex M3-based system. [ABSTRACT FROM PUBLISHER]

This paper presents a geometric-mean-decomposition (GMD) processor for multiple-input multiple-output (MIMO) communication systems. The proposed GMD processor has a flexible architecture that supports channel matrices of arbitrary dimensions. A complex-valued bi-diagonalization is proposed at the preprocessing stage, which substantially reduces the overall hardware complexity. The proposed GMD processor naturally supports an economic channel state information (CSI) feedback mechanism, rendering it highly suitable for frequency-division-duplexing (FDD) systems. To illustrate the performance of the proposed architecture, we demonstrate an efficient implementation supporting 2 to 8 spatial streams in a 90-nm CMOS technology. The latency constraint of 16 \mu\texts specified in the 802.11ac standard is adopted for this hardware realization. The chip integrates 437.7 K gates in 1.830 $\times$ 1.829 \text{mm}^{2} and dissipates 125.5 mW at 66.67 MHz from a 1 V supply. Compared with the existing GMD implementations, this work supports GMD for matrices of larger dimensions with comparable silicon area, despite the added spatial information feedback capability. [ABSTRACT FROM PUBLISHER]

Practical data detectors for future wireless systems with hundreds of antennas at the base station must achieve high throughput and low error rate at low complexity. Since the complexity of maximum-likelihood (ML) data detection is prohibitive for such large wireless systems, approximate methods are necessary. In this paper, we propose a novel data detection algorithm referred to as Triangular Approximate SEmidefinite Relaxation (TASER), which is suitable for two application scenarios: i) coherent data detection in large multi-user multiple-input multiple-output (MU-MIMO) wireless systems and ii) joint channel estimation and data detection in large single-input multiple-output (SIMO) wireless systems. For both scenarios, we show that TASER achieves near-ML error-rate performance at low complexity by relaxing the associated ML-detection problems into a semidefinite program, which we solve approximately using a preconditioned forward-backward splitting procedure. Since the resulting problem is non-convex, we provide convergence guarantees for our algorithm. To demonstrate the efficacy of TASER in practice, we design a systolic architecture that enables our algorithm to achieve high throughput at low hardware complexity, and we develop reference field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs for various antenna configurations. [ABSTRACT FROM PUBLISHER]

Modern wireless communication standards define new high-throughput use cases like 8 $\times$ 8 multiple-input, multiple-output (MIMO) antenna setups and a 256-QAM constellation alphabet in the case of IEEE 802.11ac. Baseband precoding at the transmitter is a key technique to achieve the corresponding data rates at a reasonable signal-to-noise ratio (SNR). Multimode capability, (i.e., the ability to support multiple MIMO setups) is crucial for legacy compatibility or for the adaptation to the individual configurations of mobile stations. This paper presents an application-specific integrated circuit (ASIC) template for singular value decomposition (SVD)-based linear precoding supporting multimode MIMO. A two-sided cyclic Jacobi algorithm is applied to decompose the SVD computation exclusively into 2 \times$ 2 vector arithmetic units. A fixed computation pattern is executed iteratively on the input data. Iteration control allows a graceful trading of communication performance for a reduction of computational complexity. As a proof-of-concept, the architecture template is configured to support 2 \times$ 2, 4 \times$ 4, 6 \times$ 6, and 8 and a clock frequency of 752 MHz. The achieved throughput is 188, 15.7, 6.27, and 1.68 million SVDs per second, respectively. [ABSTRACT FROM PUBLISHER]

This paper proposes a time-interleaved RF carrier modulation and demodulation technique, suitable for high frequency mixer applications under a constraint of active device speed limitation. The presents are in essence mixer arrays where modulated outputs by a series of time-delayed carriers with a reduced frequency, compared with a carrier frequency in fundamental mixers, will be interleaved in the time domain to synthesize the final output. The mixer arrays inherit an FIR filtering function, and the time interleaving process is equivalent to the filtering process where the arrays select the fundamental tone or its harmonics of a carrier in a periodic manner. The carrier waveform and duty-cycle play important roles in the noise performance of the mixer arrays. A comprehensive noise analysis is presented in this paper for both cases of correlated-noise and uncorrelated-noise mixer arrays. To minimize output noise power, optimization of carrier duty-cycle and noise filtering technique have been proposed and analyzed extensively for various types of carrier pulse. Finally analytical mismatch models are provided and output SNR degradations under finite mismatches amongst mixer array elements have been discussed based on the mismatch models. All theoretical analyses are verified through behavioral mixer array simulations including Monte-Carlo statistical simulations. [ABSTRACT FROM AUTHOR]

This paper presents a hardware-efficient architecture for 4×4 and 8×8 high-throughput MIMO detectors. The adopted non-constant K-best algorithm tends to keep more survival nodes in top search tree layers and reduce computational complexity in bottom layers as opposed to the conventional K-best algorithm. A pipelined architecture is used to generate one detection output per clock cycle, thus meeting multi-gigabit throughput requirements for advanced wireless communication systems. The proposed efficient folding scheme strikes a suitable balance between complexity and throughput. This paper also presents a discussion on the scalability of this architecture with respect to the setting of QAM size, K values, and antenna number. One 4×4 MIMO detector IC has been manufactured and one 8×8 MIMO detector layout has been realized, both in 90-nm CMOS technology. The 4×4 detector IC has 232 kilogates (KG). Its maximum measured throughput is 4.08 Gbps at 170-MHz operating frequency and 1.3-V core voltage. The 8×8 detector has 665 KG. Its post-layout simulation results show that it achieves 4.37-Gbps throughput at 182-MHz operating frequency and 0.9-V core voltage. Compared to earlier hard-output detectors, both implemented detectors demonstrate good normalized power and normalized hardware efficiencies. [ABSTRACT FROM AUTHOR]

This paper exploits the predominance of embedded memories in current and emerging wireless transceivers as a means to save power via channel state aware voltage scaling. The paper presents a statistical model that captures errors in embedded memories due to voltage over-scaling and maps the errors to a Gaussian distribution that represents a combination of communication channel noise and hardware noise. Designers can use the proposed model to investigate different power management policies, that capture the performance of the system as a function of both channel and hardware dynamics, thus creating a much richer design space of power, performance and reliability. A case study of a DVB receiver is presented and the validity of the proposed model is confirmed by simulations. [ABSTRACT FROM AUTHOR]

This paper presents the theoretical analysis and simulation results of an IF to DC subsampler for 60 GHz heterodyne receivers architectures. A particular arrangement of the frequency plan allows embedded anti-alias filtering. Down-conversion, channel filtering and IQ demodulation are merged into a unique operation at no extra cost in terms of area and power consumption. The adjacent and alternate channel rejections for the 802.15.3.c are respectively more than 15 dBc and 23 dBc thanks to charge domain subsamplers. This paper presents solutions for the implementation of the system and its integration into a complete 60 GHz receiver. Advanced analysis is made for critical points of the architecture: generation of the integration windows, IQ demodulation, noise folding and effect of clock jitter. The proposed architecture is validated by simulations and complies with the requirements of the standards for 60 GHz wireless communications. The result of this study shows that sub-sampling is suitable for high bandwidth and high data-rate receiver systems. [ABSTRACT FROM PUBLISHER]

The increasing demand for integrating multiple wireless services in one multi-standard handset, exemplified by the software-defined radio (SDR) model, calls for digitizing wireless receivers in a quest for flexibility. Radio-frequency (RF) front-end and analog baseband filters need to be exchanged for digital processing at the expense of a highly challenging analog-to-digital converter (ADC) specifications. In this paper, the sensitivities of continuous-time (CT) delta-sigma (\Delta \Sigma) ADCs, which are candidate architectures for multi-standard receivers and SDRs, to out-of-band (OOB) blockers at the ADC input are investigated. This analysis addresses the problems and performance limitations that can result from large OOB blockers appearing at the input of CT \Delta \Sigma modulators in a digitized multi-standard receiver. Analysis and discussions given in different sections of the paper are verified by CT system-level simulations. [ABSTRACT FROM PUBLISHER]

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50∼\Omega load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper. [ABSTRACT FROM AUTHOR]

This paper presents a wireless-powering current-sensing readout system on a CMOS platform for portable electrochemical measurement. The wireless sensing system includes energy-efficient power management circuitry, a sensor readout interface, and a backscattering wireless communication scheme. For power-and-area-constrained bio-sensing applications, the proposed readout circuitry incorporates an ultra-low-power potentiostatic system that generates a current according to the electrochemical reaction, as well as an oscillator-based time-to-digital converter instead of a voltage-domain analog-to-digital converter. To avoid a bulky battery and power-hungry clock reference, the chip is wirelessly powered and injection-locked by the modulated radio waves, which includes a 918 MHz carrier signal mixed with a 3.2 MHz modulated signal. The chip, implemented using a 0.18-\mu\textm CMOS process, occupies a silicon area of 1 \textmm^2. The proposed design achieves a sensitivity of 289 Hz/nA and an R^2 linearity of 0.997 over a current range of 200 nA while consuming 2.2 \mu\textW at a supply voltage of 0.8 V. The chip, integrated with a PCB antenna, has minimum sensitivities of $-$12 dBm and $-$25 dBm for RF-powering and injection-locking mechanisms, respectively. [ABSTRACT FROM PUBLISHER]

Continuous phase modulation (CPM) is widely employed in digital communication systems due to its high spectral efficiency. The main digital implementations originate in the well-known ROM-based approach. In this approach, the memory size may be very large and depends completely on the modulation parameters. This means that supporting several modulation types would require a proportional increase on the memory resources. In this paper, a new versatile single $h$ and multi- $h$ CPM transmitter is introduced, which can be reconfigured for handling any kind of CPM waveform without noticeable increase in memory. A complete digital architecture is also provided. This represents a truly reconfigurable CPM transmitter, which can be used for software defined radio platforms. Implementation results show that in data rates of more than 20 Mbps as required by the IRIG-106-15 standard, the proposed approach yields a savings of around 1.5 megabits of memory when compared to the ROM approach, at the expense of requiring 15 multipliers. Additionally, for medium-rate implementations as required in the Bluetooth standard, the proposed transmitter offers a savings of about 50 Kbits of memory while requiring only two multipliers. Simulation results confirm that the signals produced by this new approach match those expected from theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a 4 \times 4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high-throughput wireless communication systems. The receiver uses bandwidths of 40, 80, and 160 MHz that correspond to three operation modes of 128, 256, and 512-point FFT, respectively. Four spatial streams are supported to offer the maximum uncoded data rate of 2.6 Gbps. Channel pre-processing based on sorted QR decomposition and the non-constant K-best soft-output MIMO detector are adopted to enhance the system performance. The addressing scheme for the QR phase memory is proposed to deal with the processing-time discrepancy between the write-in and read-out accesses. The high-throughput pipelined architecture for the non-constant K-best soft-output MIMO detector with selected discard-paths is analyzed to show a balance between performance and complexity. This receiver IC integrates 1.034 M logic gates as well as a total of 835 Kb SRAM in 90 nm CMOS technology and can generate hard output for 64-QAM constellation. The coded system performance is also provided with the soft-output MIMO detection. From the measurement results, the power consumption of the chip is 424 mW, 97 mW, and 26 mW at 1.16 V, 0.8 V and 0.66 V, respectively, for operations in 160 MHz, 80 MHz, and 40 MHz bandwidth modes. Compared to the prior works for 80 MHz channel bandwidth, this work supports wider channel bandwidth and achieves higher throughput. [ABSTRACT FROM AUTHOR]

This paper presents a high-throughput, area-efficient and energy-efficient iterative detection and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems. A layered non-resetting IDD technique is used to minimize the number of inner iterations for a required error performance. An area-efficient minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is devised to simplify matrix inversion. A detector-decoder interface that is used to exchange soft messages efficiently is proposed. Given the throughput specifications, inner and outer loops are optimally combined to maximize the error performance. The design specifications defined in the IEEE 802.11n standard are adopted as the design target. A 4 \times 4 antenna configuration with BPSK, QPSK, 16-QAM modulations are realized in silicon. The designs that support 64-QAM and 256-QAM modulations are also demonstrated for comparison with prior work. Fabricated in 40 nm technology, the chip integrates 998k logic gates in 1.33 mm^2 and achieves a maximum throughput of 794 Mb/s. The chip dissipates 135 mW at 0.9 V, achieving an energy efficiency of 170 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper explores the extent to which a solid-state transmitter can be miniaturized, while still using RF for wireless information transfer and working with power densities and operating voltages comparable to what could be harvested from a living system. A 3.1 nJ/bit pulsed millimeter-wave transmitter, 300 \mum by 300 \mum by 250 \mum in size, designed in 32-nm SOI CMOS, operates on an electric potential of 130 mV and 3.1 nW of dc power. Far-field data transmission at 33 GHz is achieved by supply-switching an LC-oscillator with a duty cycle of 10^-6. The time interval between pulses carries information on the amount of power harvested by the radio, supporting a data rate of \sim1 bps. The inductor of the oscillator also acts as an electrically small (\lambda/30) on-chip antenna, which, combined with millimeter-wave operation, enables the extremely small form factor. [ABSTRACT FROM PUBLISHER]

Recently, an ultra-wideband (UWB) system with frequency-modulated differential chaos shift keying (FM-DCSK) modulation has attracted increasing interest for its many distinctive superiorities over its conventional counterparts, especially in low-rate and low-power wireless personal area network (WPAN) applications. However, some of its drawbacks, such as low energy efficiency, complex implementation and weak multiaccess capacity, have also been noticed, which restrict its further acceptance and applications. To overcome these problems, an architecture, named single-input and multiple-output (SIMO) FM-DCSK UWB system, is introduced in this paper. With chaotic transmitted signals based on a high-order Walsh function and multiple antennas diversity reception, this paper demonstrates the superiorities of the new system in bit error rate (BER) performance as well as in moderation complexity. Furthermore, by transmitting chaotic pulse cluster signals, an improved emission signal structure of the SIMO FM-DCSK UWB system is proposed so as to overcome the delay line implementation constraints and to further enhance the BER performance. Based on this new signal format, a method of combining time division and Walsh function division is introduced into the existing Walsh function division scheme, thereby resolving the inherent obstacle in user capability which was known to be limited by the order of the Walsh function. [ABSTRACT FROM PUBLISHER]

This paper introduces a new modulation technique, called pulse harmonic modulation (PHM), for wideband, low power data transmission across inductive telemetry links that operate in the near-field domain. The use of sharp and narrow pulses, similar to impulse-radio ultrawideband (IR-UWB) in the far-field domain, leads to significant reduction in the transmitter power consumption. However unlike IR-UWB, where all pulses are the same, in PHM each bit consists of a pattern of pulses with specific time delays and amplitudes, which minimize the intersymbol interference (ISI) across the receiver coil. This helps achieve a high data rate without reducing the inductive link quality factor and selectivity, which are necessary to block interferers. The received signal consists of an oscillation pattern that is amplitude modulated by the amplitude and timing of the successively transmitted pulses to facilitate data demodulation with low bit-error rate (BER). The main application of the PHM is expected to be in the neuroprostheses, such as brain–computer interfaces (BCIs) or cochlear/retinal implants, which need to transfer large volumes of data across the skin. It may also be used in short-range proximity-based digital communications with high-throughput wireless devices. This paper describes the PHM theoretical foundation and demonstrates its operation with a proof-of-concept prototype setup, which achieves a data rate of 5.2 Mbps at 1 cm coil separation with a BER of 10^- 6. [ABSTRACT FROM PUBLISHER]

This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multiple inputs required for row layered processing of hardware-friendly min-sum decoding algorithm. The results show good speed with lower area as compared to state-of-the-art circuits. Additionally, this work proposes dynamic multi-frame processing schedule which efficiently utilizes the layered-LDPC decoding with minimum pipeline stages. The suggested LDPC-decoder architecture has been synthesized and post-layout simulated in 90 nm-CMOS process. This decoder occupies 5.19 mm^2 area and supports multiple code rates like 1/2, 2/3, 3/4 & 5/6 as well as block-lengths of 648, 1296 & 1944. At a clock frequency of 336 MHz, the proposed LDPC-decoder has achieved better throughput of 5.13 Gbps and energy efficiency of 0.01 nJ/bits/iterations, as compared to the similar state-of-the-art works. [ABSTRACT FROM AUTHOR]

In this paper, we propose a Stochastic iterative multiple-input multiple-output (SIM) detection system based on the Markov chain Monte Carlo (MCMC) method. To improve the detection performance, the Gibbs sampler of the MCMC detector in the SIM is updated by the decoded bits from a channel decoder directly. The channel decoder is part of the updating unit that generates the new samples in the MCMC updating process. We also implement the SIM in a fully parallel scheme, which achieves a high detection speed. As a case study, we have designed and synthesized a 128-parallel 4\times4 16-QAM SIM system using a CMOS 130 nm technology with a core area of 1.98 mm^2 and 457K logic gates. The SIM detection system can achieve a throughput of 787.5Mbps with a frame error rate (FER) 10^-3 at Eb/N0=7dB, equaling the FER of a traditional iterative MIMO detection with four outer iterations. [ABSTRACT FROM AUTHOR]

This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-speed short-range wireless communications such as wireless network-on-chip (WiNoC) applications. Targeting at data rates of beyond 16 Gb/s, the OOK demodulator consists of a wideband envelope detector (ED) and a single-stage baseband (BB) peaking amplifier. Novel dual gain-boosting techniques improve the gain, bandwidth, and out-of-band rejection of the ED. In addition, an actively-enhanced tunable inductor (AETI) load in the BB amplifier not only significantly reduces its area overhead, but also provides a tunable peaking level. Fabricated in a 65-nm bulk CMOS process, the OOK demodulator consumes only 4.6 mW from a 1-V supply, and occupies an active area of 0.043 mm^2. A maximum data rate of 18.7 Gb/s with a bit-error rate less than 10^-12 is demonstrated through measurements, which translates to a bit-energy efficiency of 0.25 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of the proposed design is close to the existing maximum likelihood post-detection processing (ML-PDP) scheme, while resulting in a significantly lower complexity, i.e., 4.5\times 10^2 and 7\times 10^4 times fewer Euclidean distance (ED) calculations in the 16-QAM and 64-QAM schemes, respectively. The proposed design for the 16-QAM scheme is fabricated in a 0.13\mum CMOS technology and fully tested, achieving a 1.332 Gbps throughput, reporting the first fabricated design for SC-FDMA MIMO detectors to-date. A soft version of the proposed architecture is also introduced, which is customized for coded systems. [ABSTRACT FROM AUTHOR]

This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 mm^2 core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 \times 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. [ABSTRACT FROM AUTHOR]