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The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nVrms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%. [ABSTRACT FROM AUTHOR]

This paper presents various techniques to achieve high efficiency for the bidirectional Cascaded-Buck-Boost converter. This converter has the features of low voltage across the switches and positive output voltage. The objective of this paper is to optimize the magnetics design to reduce the total losses in a low power non-isolated DC-DC circuit. A rigorous loss model with component nonlinearities is developed to determine the power loss distribution. It is validated by simulations and experiments. Based on the results of the power loss analysis and due to the low inductor profile and high efficiency target, nanocrystalline material will be the best candidate. Therefore, a new small volume low profile planar-nanocrystalline inductor is designed. Various deep de sign aspects for core and copper are discussed. The Finite-Element-Analysis (FEA) method is used to examine and visualize the inductor design. By implementing the planar-nanocrystalline inductor, a California Energy Commission (CEC) weighted efficiency of 99.05% for the buck mode and 98.98% for the boost mode are achieved with a peak efficiency of 99.24% and 99.21%, respectively. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3–12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved. [ABSTRACT FROM AUTHOR]

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ($SS_{avg}$), off current (${I} _{OFF}$), and on current (${I} _{ON}$) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope. [ABSTRACT FROM AUTHOR]

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

This paper presents an active rectifier operating at 40.68 MHz for wirelessly powered biomedical implant devices. The commonly used current-injection-based compensation and delay-based compensation schemes are analyzed. To tackle design difficulties at high frequency, a hybrid delay-compensation scheme is proposed to compensate for the turn-on and turn-off delays. The proposed scheme has a simple control logic that results in a power-efficient comparator design. A fully integrated active rectifier was fabricated in a standard 0.18- $\mu \text{m}$ CMOS process with a total area of 1.581 mm2 and a maximum output power of 56.6 mW. With the input ac voltage ranging from 2.5 to 4 V and the load resistor ranging from $200~\Omega $ to 2 $\text{k}\Omega $ , the measured peak voltage conversion ratio and peak power conversion efficiency reach 91% and 80.9%, respectively. [ABSTRACT FROM AUTHOR]

Highly efficient switch-mode class-E power amplifiers (PAs) are sensitive to load impedance variations. For voltage standing wave ratios (VSWRs) up to 10:1, the peak switch voltage and the average switch current can increase by a factor of 1.7 and 2.5, respectively, relative to those under nominal load conditions, imposing serious reliability risks. This paper describes a technique to self-protect class-E PAs to decrease their sensitivity to load variations, relying on the tuning of the switch-tank relative-resonance frequency, implemented by an on-chip switched-capacitor bank (SCB). To validate the technique, load-pull measurements are conducted on a class-E PA implemented in a standard 65-nm CMOS technology, employing an off-chip matching network, augmented with a fully automated self-protective control loop. Under nominal conditions, the PA provides 17.8 dBm at 1.4 GHz into $50\,{\Omega }$ from a 1.2-V supply with 67% efficiency. The proposed self-protective PA can reduce its peak switch voltage below the technology- and switch design-related limit for any load with a VSWR up to 19:1 while not considerably impacting output power and efficiency, which see a maximum degradation of 1.6 dB and 6%, respectively. Furthermore, a class-E PA designed to safely handle $2.5{\times }$ the nominal average switch current can reliably operate for VSWRs up to 19:1 when protected with our technique. [ABSTRACT FROM AUTHOR]

As an emerging nonvolatile device, ferroelectric field-effect transistors (FeFETs) have the potential to reduce the power and area by integrating nonvolatile storage elements with logic. The hysteretic behavior allows an FeFET to function as both a nonvolatile storage element and a switch. This paper exploits this feature of FeFETs to design lookup tables (LUTs) and routing switches, which have obvious utility in field-programmable gate arrays (FPGAs). Read and write schemes are also designed for the proposed LUTs and routing switches. Evaluation results based on a calibrated FeFET model show that the proposed designs are competitive in power and performance. For example, compared with conventional complementary metal–oxide–semiconductor (CMOS)-based equivalents, the proposed FeFET-based LUTs and routing elements improve the power-delay product (PDP) by 5.8– $16\times $ , respectively, while compared with resistive random-access memory (RRAM)-based equivalents, the proposed designs improve the PDP by 1.14– $1.8\times $. The area of an FeFET-based FPGA is 8% smaller than a conventional CMOS-based FPGA. [ABSTRACT FROM AUTHOR]

This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is $0.291 \times 1.457\,\,\mu \text{m}^{2}$. The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme. [ABSTRACT FROM AUTHOR]

Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves. [ABSTRACT FROM AUTHOR]

Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars. The functions are realized as a netlist of NOR and NOT gates. Two alternate methods of evaluating the gates are used, serial and parallel, which give a tradeoff between the number of cycles and the size of the crossbar. A strategy for scheduling the gates to time steps has also been proposed to reduce the hardware overhead. The switching delays and energy requirements are estimated using SPICE simulation. Synthesis results are reported for ISCAS’85 benchmark functions that show an average reduction of 68.8% in the number of cycles, 52.8% in energy consumption, and 96.4% in the number of memristors required as compared to a very recently published work. [ABSTRACT FROM AUTHOR]

Wiring is one of the main challenges in aircrafts. The avionics industry is exploring new schemes to minimize the number of power and data cables to build lighter, more reliable and fuel-efficient aircrafts. In this paper, we describe a novel integrated power harvesting interface to procure power required for avionic sensors. The implemented power harvesting approach is based on a modified power over Ethernet scheme in which the power in the ARINC 825 field (data) bus during its idle times serves as the source for the power conversion chain. A transistor-level design is carried out in CMOSP 0.35 \mu \textm (AMS) 3.3 V/5 V technology and the system performance is investigated under various conditions to improve its efficiency. From the experimental tests, an overall efficiency of 60 % was achieved and the harvesting device provided an output power of 10.08 mW for feeding sensors. Reported experimental results proved that the proposed power recovery scheme could serve as a power recovery unit to supply embedded sensors. [ABSTRACT FROM PUBLISHER]

Resistive RAM (RRAM) technologies are gaining importance due to their appealing characteristics, which include non-volatility, small form factor, low power consumption, and ability to perform logic operations in memory. These characteristics make RRAM highly suited for Internet of Things devices and similarly resource-constrained systems. This paper proposes a novel memristor-based xnor gate that enables the execution of xnor/xor function in the memristive crossbar memory. The proposed two-input xnor gate requires two steps to perform the xnor function. The design of the circuit utilizes bipolar and unipolar memristors and permits cascading by only adding an extra step and one computing memristor. To the best of our knowledge, this is the first native stateful xnor logic implementation. Spice simulations have been used to verify the functionality of the proposed circuit. This includes benchmarking the proposed design against the state-of-the-art stateful memristor-based logic circuits. The results for implementing three-input xor using the proposed circuit demonstrate efficient performance in terms of energy, latency, and area. The gate shows 56% saving in energy, 54% less number of steps (latency), and 50% less number of computing MR (area) compared with the state-of-the-art stateful xor/xnor implementations. [ABSTRACT FROM PUBLISHER]

In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies. [ABSTRACT FROM AUTHOR]

This paper presents a circuit in which tungsten oxide -based analog memristors are post-processed on a CMOS-based Field-Programmable Analog Array Integrated Circuit (FPAA-IC). FPAAs are powerful tools for rapid analog experimentation, prototyping and power-efficient computing, and they allow custom analog circuits to be built and reconfigured. The primary motivation for this work is to introduce and demonstrate the operation of the FPAA/memristor hybrid circuit and the board-level infrastructure, and to form a basis for subsequent empirical work on analog memristive computing. The experiments shown in this paper demonstrate a successful fabrication of memristors on the FPAA substrate, and the usefulness of the hybrid computing infrastructure in terms of experimentation with memristors. The experiments suggest that a single state variable cannot capture the adaptation of a memristor. To this end, a SPICE compatible memristor model with two state variables is presented. Furthermore, a memristor-based adaptive coincidence detector is demonstrated on the FPAA/Memristor computing infrastructure. [ABSTRACT FROM AUTHOR]

In this paper, we propose a design of traditional sequential circuits using high performance Ballistic Deflection Transistor (BDT). BDT technology was developed and experimentally proven to operate at Terahertz frequencies. Different structures of BDTs have been developed successfully to realize combinational logic functionality. Monte Carlo (MC) simulations have been extensively used to study these structures. By taking into account the effect of surface charges and dielectrics, we are able to correctly reproduce the non-linear I-V transfer characteristics, to predict scaling down behavior and to estimate the very high switching speed. We then used a three parameter Gaussian peak as a predictive model for the BDT and integrated it with Verilog AMS module to confirm the functionality of the designed circuits. Finally, we used a recently developed level-sensitive D-latch using two-BDTs structure, to explore traditional sequential circuits such as Shift Registers (SRs), Frequency Divider and Johnson Ring Counter, which play a pivotal role in many processing systems as common datapath operators. The simulation results have indicated the correct logic functionality of the implemented sequential circuits. [ABSTRACT FROM PUBLISHER]

This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1 V, 0.8 V, and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 \mu\textA to 800 \mu\textA. The switched-capacitor converter is designed and fabricated in 65-nm low-power CMOS technology and occupies an area of 0.493 mm2. The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80% at a load current of 800 \mu\textA and regulated load voltage of 1 V. [ABSTRACT FROM PUBLISHER]

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 28 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities. Extensive Monte Carlo and voltage scaling simulations are performed to show that the presented designs are robust under PVT variations. [ABSTRACT FROM PUBLISHER]

The mutual exclusion element is a fundamental component of asynchronous arbiters. Despite their importance, however, the testability of these components is typically limited to functional testing. This paper discusses why this is not sufficient and investigates three MUTEX implementations, two of which are completely new, that support the test of the metastability filter part of the components. Additionally, we quantify the cost of the testable designs by comparing them to a baseline design in terms of failure rate, impact on MTBF, propagation delay, test power and area. Our experimental results show that testable MUTEXes increase area from 21% to 63% over the baseline implementation, but have a small impact on delay and provide a range of choices where testability, MTBF, test power and area can be traded-off against circuit and system requirements. [ABSTRACT FROM PUBLISHER]

Field Programmable Gate Arrays (FPGAs) can benefit non-volatility and high-performance by exploiting Resistive Random Access Memories (RRAMs). In RRAM-based FPGAs, the memories do not only replace the SRAMs and store configurations, but they can also replace the transmission gates and propagate datapath signals. The high-performance achievable by RRAM-based FPGAs comes from the fact that the on-resistance of the memory devices R_\mathrmLRS is smaller than the equivalent resistance of a transmission gate. Efficient programming structures for RRAMs should provide high current density with a small area footprint, to obtain a low R_\mathrmLRS. In this paper, we first examine the efficiency of the widely-used 2Transistor/1RRAM (2T1R) programming structure and identify four major limitations of the 2T1R structure. To overcome these limitations, we propose a 2Transmission-Gates/1RRAM (2TG1R) and a 4Transistor/1RRAM (4T1R) programming structures. We perform both theoretical analysis and electrical simulations on the evaluated programming structures. 4T1R programming structure is the best in terms of current density with 1.4 \times and 1.1 \times as compared to 2T1R and 2TG1R counterparts, respectively. We also investigate the effect of boosting the programming voltage V_\mathrmprog of the programming structures. Experimental results show that boosting V_\mathrmprog for all the programming structures improves driving current of the evaluated programming structures by 3 $\times$ and area efficiency by 1.7 $\times$ on average. [ABSTRACT FROM AUTHOR]

Recently, it has been demonstrated that memristors can be utilized as logic gates, control switches as well as memory elements. In this paper, we analyze the different AND, OR, and NOT logic gates which are based on memristors. In addition, a novel design for a memristor-based switch is presented, which can be used in the peripheral read/write circuits of the memristor-based memory. Moreover, methods of consecutive read with long refresh intervals and fast write for the proposed design are also discussed. Another highlight of this work is the analysis of the proposed memristor-based crossbar architecture which has a series of excellent features, such as good-compatibility, high-density, non-volatility, low-power, and good-scalability. Simulation results also show that the proposed memory array has superior performances compared to other memristor-based arrays proposed in the existing technical literature. [ABSTRACT FROM AUTHOR]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a complete transmitter prototype for wireless applications using envelope tracked pulsed gate modulated power amplifier (PA). The proposed transmitter architecture is developed using two high power 10 W gate modulated PAs combined in a fashion to operate as a switched voltage source for the range of duty cycles of pulses driving the gates of power amplifiers. These PAs are designed and implemented using packaged GaN HEMT transistors from CREE to operate at the carrier frequency of 2.35 GHz. For a 5 MHz bandwidth WiMAX 802.16e down-link signal with the PAPR of 7.9 dB and the oversampling ratio of 100, the average drain efficiency of 46.2% is achieved at the average output power of 35.8 dBm. Using a 5 MHz bandwidth LTE down-link signal with 11 dB PAPR and centered at 2.35 GHz, the power amplifier delivers the average output power of 33.2 dBm with the average drain efficiency of 46%. The adjacent channel leakage ratio (ACLR) measured for this signal is less than -36.85 dBc at 10 MHz offset from the center frequency of 2.35 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency zero-voltage- switching (ZVS) AC-DC light-emitting-diode (LED) driver. The structure of the proposed converter is based on a buck-boost power-factor-correction (PFC) converter. Through replacement of an output diode with a self-driven synchronous rectifier (SR), the conduction loss decreases significantly, and there is no switching loss because of the ZVS operation of the switching devices. In addition, no additional control circuit is required and cost reduction is achieved because the SR is self-driven. The efficiency of the proposed converter is higher than that of the conventional critical-conduction-mode (CRM) buck-boost PFC converter, owing to the reduced conduction loss of the high-side output rectifier and no switching loss of either of the switches. For verifying the ZVS operation and efficiency improvement of the proposed AC-DC LED driver, theoretical analysis and experimental results of a 48-[V] and 1.4-[A] prototype for LED driver are discussed. [ABSTRACT FROM AUTHOR]

This work presents a low noise active pixel sensor. It uses one additional transistor compared to standard 4T pixel to obtain 1/f noise reduction and high conversion gain. 1/f noise is reduced by periodically switching the in-pixel source follower between depletion and inversion. The depletion state is achieved by re-configuring the source follower into a MOS capacitor and depleting the channel by controlling the source-drain terminal. The state change of the in-pixel source follower also enhances the conversion gain. The test chip has a $64 \times 64$ pixel array with a $10~ {\mu }\text{m}$ pixel pitch fabricated in 350 nm AMS process. The measured integrated noise of a pixel in the frequency band 128 Hz to 50 KHz is $728~ {\mu V_{rms}}$ without switching. At a switching frequency of 4 MHz, the integrated noise reduces to $306~ {\mu V_{rms}}$ after switching resulting in a 7.5 dB reduction. The input referred noise is reduced from $26 {e_{rms}^{-}}$ to $7.3 {e_{rms}^{-}}$ after applying switching. When both, switching and conversion gain enhancement are applied, the input referred noise is further reduced to $2.3 {e_{rms}^{-}}$ with an enhanced conversion gain of $398\,\, {\mu V/e^{-}}$. [ABSTRACT FROM AUTHOR]

This work presents a novel path balanced masked dual-rail pre-charge circuit design scheme based on binary decision diagrams (BDD), using one mask bit per output. It has been applied for achieving masked implementations of two common lightweight ciphers, namely Present and Lucifer. BDD based logic design is achieved using the CUDD tool and applying suitable variable reordering techniques. Path balancing has helped to counter the early propagation effect (EPE) to achieve a glitch free circuit design. Non-linear shift register has been used to generate the mask bits to avoid prediction of the mask bit, even if those should be occasionally uncovered. The design has been evaluated on many aspects such as glitch attack resistance, correlation / differential power analysis attack resistance, peak power variance, etc. and found to have satisfactory circuit performance while being highly robust to side channel attacks. [ABSTRACT FROM AUTHOR]

This article presents Switched-Capacitor assisted Power Gating (SwCap PG) for reducing the leakage currents of large digital circuits. For the first time, PG switch is biased in the super turn-off and the super turn-on mode during the off-state and the on-state, respectively. A simple switched-capacitor network reconfigures and biases the PG switch in four different possible states with low area and power overhead. During the super turn-off, voltage stress is avoided in the PG switch when the circuit load uses supply voltage equal to the nominal $\text{V}_{\mathbf {DD}}$ in a given technology, and maximum possible leakage current reduction is achieved by the optimal biasing of the gate voltage. The proposed SwCap PG is experimentally validated in the 180nm CMOS technology. Measurement results of CMOS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by 186- $226\times $ and 18% respectively, as compared to the conventional PG. An alternate solution for SwCap network using MEMS devices as the switching elements is implemented for additional benefits. Measurement results of MEMS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by $172\times $ and 26% respectively, compared to the conventional PG. Finally, the applicability of the SwCap PG in the nano-scale CMOS technologies is addressed. [ABSTRACT FROM AUTHOR]

The conditional switching of memristors to execute stateful implication logic is an example of in-memory computation to potentially provide high energy efficiency and improved computation speed by avoiding the movement of data back and forth between a processing chip and memory and/or storage. Since the first demonstration of memristor implication logic, a significant goal has been to improve the logic cascading to make it more practical. Here, we describe and experimentally demonstrate nine symmetry-related Boolean logic operations by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices, i.e., a particular device is switched depending on the state of another device. We introduce a family of four stateful two-memristor logic gates along with the copy and negation operations that enable two-input-one-output complete logic. In addition, we reveal five stateful three-memristor gates that eliminate the need for a separate data copy operation, decreasing the number of steps required for a particular task. The diversity of gates made available by simply applying coordinated sequences of voltages to a memristor crossbar memory significantly improves stateful logic computing efficiency compared to similar approaches that have been proposed. [ABSTRACT FROM AUTHOR]

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) R\mathrm{\scriptscriptstyle ON} -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and measurement results establish the accuracy of the analysis. Since the three sources of distortion each have a unique dependence on circuit parameters and the input signal frequency, a systematic method is shown to optimize an S/H circuit for least distortion. [ABSTRACT FROM AUTHOR]

A high-speed dynamic biasing technique is presented for reducing op amp power in discrete-time, multistage, analog circuits employing op amp sharing. To exploit typical power scaling in such circuits, a charge pump, of which the on-times of up and down currents are controlled by two comparators, performs rapid change of the op amp bias condition between a low-current mode and a high-current mode during nonoverlapping clock periods of the two phase clocks. The errors caused by finite comparator delay are compensated for by embedding intentional offset voltages in the comparators, which are implemented by using asymmetric differential input pairs in the comparators. To verify the efficacy of the proposed biasing technique, an 11-b pipelined analog-to-digital converter (ADC) has been implemented using 0.15- \mu \textm devices in a 28-nm CMOS technology. With a 20-MHz sampling clock, the ADC achieves a 61.8-dB SNDR while consuming a 2.24-mW power from a 1.8-V supply. The MDAC and ADC power are reduced by about 45% and 30%, respectively, compared with a conventional pipelined ADC employing an op amp in each MDAC. Owing to the simple structure of the proposed dynamic biasing, the prototype ADC occupies only 0.052 mm2. [ABSTRACT FROM AUTHOR]

Sustaining of Moore’s Law over the next decade will require not only continued scaling of the physical dimensions of transistors but also performance improvement and aggressive reduction in power consumption. Heterojunction Tunnel FET (TFET) has emerged as promising transistor candidate for supply voltage scaling down to sub-0.5V due to the possibility of sub- $kT$ /q switching without compromising on-current (ION). Recently, n-type III-V HTFET with reasonable on-current and sub-kT/q switching at supply voltage of 0.5V have been experimentally demonstrated. However, steep switching performance of III-V HTFET till date has been limited to range of drain current ( \text {I}_{\mathrm {DS}} ) spanning over less than a decade. In this work, we will present progress on complimentary Tunnel FETs and analyze primary roadblocks in the path towards achieving steep switching performance in III-V HTFET. [ABSTRACT FROM PUBLISHER]

An energy-efficient fast array multiplier is proposed and designed. The multiplier operates in a left-to-right mode enabling a full overlap between reduction of partial products in carry-save form and the final addition producing the product. The design is based on the left-to-right carry-free (LRCF) multiplier. It differs from the LRCF multiplier in a much smaller on-the-fly conversion circuit of $O(n)$ size and the use of radix-4 full adders in the conversion. The new converter produces the most-significant half of the product during the reduction process. It eliminates the most-significant part of the final adder. The least-significant half of the product is obtained with a carry-ripple adder during the reduction. Thus conversion of the carry-save form of accumulated partial products to the conventional product does not add any delay to the total time of the multiplier. Several right-to-left, left-to-right multipliers and tree multipliers are designed for 16, 24, 32, and 56 bits, and radices 2 and 4, synthesized in 90 nm technology and compared, demonstrating the advantages and disadvantages of the proposed design with respect to area, delay, power, and energy. We considered both truncated and full-precision multipliers. The proposed multiplier has lower delay, area, power, and energy than other considered types of array multipliers. Its advantages grow with the increase in precision. As expected, it is slower than a tree multiplier but it has smaller area, power, and energy. [ABSTRACT FROM PUBLISHER]

A high efficiency, maximum power point tracking (MPPT) power management unit (PMU), with 3.6 \mmb\mu\bf W quiescent power, aimed at a thermoelectric generator (TEG) array is presented. The proposed energy harvesting PMU is made up of a boost converter with a cascaded capacitor-less low drop-out (CL-LDO) voltage regulator. The segmented approach allows the PMU to match the TEG array's changing dynamic series resistance via the boost converter and simultaneously provide voltage regulation with adaptive, high switching noise rejection via the CL-LDO. The boost converter's switching frequency (f{sw}) is tracked via a Sense-and-Control loop which modifies the CL-LDO's power supply rejection (PSR) characteristics to place a notch in the PSR transfer function around the average f{sw}. Experimental results show an overall system efficiency better than 57% @ 1.6 V output voltage, PSR of 40 dB at f{sw}, and a notch-tuning range of 15–65 kHz. The total active area is 0.93 mm^2 in 0.5 \mum CMOS. [ABSTRACT FROM PUBLISHER]

A self-sustainable sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. An ultra-low power chip featuring an ARM Cortex-M0 processor, 3 kB of SRAM, and power management unit (PMU) is designed to consume 11 nW in sleep mode for perpetual sensing operation. The PMU includes a switched-capacitor DC/DC converter designed for efficient energy harvesting and step-down conversion for a wide range of input and output power. A small-scale MFC with 21.3 cm^2 anode surface area was connected to the PMU to charge a thin-film battery of 1 mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1-s wake-up time demonstrated the sustainability of system-on-mud concept. During sleep mode operation, the system charges the 4 V battery at 380 nA from the micro-MFC generating 5.4 \muW of power, which allows up to 20 mA of active mode current with net energy neutrality. [ABSTRACT FROM AUTHOR]