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In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents a new family of conditioning circuits used in electrostatic kinetic energy harvesters (e-KEHs), generalizing a previously reported conditioning circuit known as the Bennet's doubler. The proposed topology implements a conditioning scheme described by a rectangular charge-voltage cycle (QV-cycle) of tunable aspect ratio. These circuits show an exponential increase of the converted energy over operation time if studied in the sole electrical domain. The QV-cycle's aspect ratio can be set to values that were previously inaccessible with other exponential conditioning circuits. After a brief intuitive presentation of the new topology, its operation is rigorously analyzed and its dynamics are quantitatively derived in the electrical domain. In particular, the aspect ratio of the rectangular QV-cycle describing the biasing scheme of the transducer is expressed as a function of the circuit's parameters. Practical considerations about the use of the reported conditioning circuits in actual e-KEHs are also presented. These include a discussion on the applications of the proposed conditioning, a description of the effects of electrical nonidealities, and a proposition of an energy extracting interface. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a fully-integrated reconfigurable charge pump in a 0.18- $\mu \text{m}$ CMOS process; this converter is applicable for self-powered Internet-of-Things applications. The proposed charge pump uses a two-dimensional frequency modulation technique, which combines both the pulse-frequency modulation (PFM) and pulse-skip modulation (PSM) techniques. The PFM technique adjusts the operating frequency of the converter according to the variations in the load current, and the PSM technique regulates the output voltage. The proposed two-dimensional frequency modulation technique can improve the overall power conversion efficiency and the response time of the converter under light load conditions. A photovoltaic cell was chosen as the input source of the proposed converter. To adapt to the variations in the output voltage of a photovoltaic cell under different light illumination intensities, we built a reconfigurable converter core with multiple power conversion ratios of 2, 2.5, and 3 for the regulated output voltage of 1.2 V when the input voltage ranged from 0.53 V to 0.7 V. Our measurement results prove that the proposed capacitive power converter could achieve a peak power conversion efficiency of 80.8%, and the efficiency was more than 70% for the load current that ranged from $10~\mu \text{A}$ to $620~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

This paper employs a time-variant model to determine the exact small-signal loop transmission of second-order charge-pump phased-locked loops. The model predicts that a loop bandwidth of close to half the input frequency can be achieved. The large-signal behavior is also analyzed and two modes of oscillation are identified. The results are confirmed by means of circuit simulations. [ABSTRACT FROM PUBLISHER]

This paper presents an optically-powered wireless tag, integrating a charge pump (CP) and a low-power RF transmitter for batteryless Internet-of-Things (IoT) applications. The proposed charge pump with hysteresis regulation mechanism (HRM) powers the transmitter circuit using indoor light energy. The charge pump enables the transmitter whenever the output capacitor stores sufficient energy and guarantees a short period signal transmission. The proposed low-power transmitter contains the subharmonically injection-locked PLL and the capacitive coupling technique to achieve a large frequency multiplication ratio. The proposed batteryless wireless chip is fabricated in 0.18- $\mu \text{m}$ CMOS process. The measurement results demonstrate that the proposed charge pump provides a 1.1 to 1.3 V hysteresis regulated voltage under indoor light illumination larger than 300 lux. The charge pump achieves 84.1% peak efficiency and the communication distance of 3 meters is demonstrated while only consuming $248~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

An inductive power converter for thermoelectric generator (TEG) is presented in this paper. A novel redundant inverter ring oscillator is proposed to self-oscillate in a very low supply voltage down to 45 mV. An additional self-start assist circuit with a differential clock booster and an exponential charge pump is implemented in the power converter to achieve lower self-start voltage. Boundary continuous-conduction mode, zero current switch (ZCS), and maximum power point tracking (MPPT) features have been incorporated into the power converter. Selective turn-ON dynamical-comparators have been used in ZCS and MPPT circuits to save power and achieve minimum operating supply voltage. Fabricated in 65-nm CMOS process, the chip can self-start at 210 mV. After self-start, only 7-mV input voltage is needed to sustain the power converter operation. With a TEG open circuit voltage of 80 mV and internal resistance of $5~\Omega $ , the chip can provide a maximum output power of 229~\mu \text{W} with end-to-end efficiency of 71.5%. [ABSTRACT FROM PUBLISHER]

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesired charge transfer, thereby improving power efficiency and increasing output voltage effectively. An optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. Simulations of 8-stage charge pumps in a 0.13~\mu \textm standard CMOS technology show that for an input supply voltage of 1.2 V, the proposed charge pump circuit reaches a power efficiency of 58.72% with an output voltage of 7.45 V, when delivering 5-mA load current, and is able to maintain a power efficiency of around 50% and an output voltage of over 5 V as the load current increases to 10 mA. Compared with the other charge pump circuits, the simulation results demonstrate better performance of proposed charge pump circuits in terms of both voltage pumping gain and power efficiency. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

In this paper a fairly complete mathematical model of CP-PLL, which reliable enough to serve as a tool for credible analysis of dynamical properties of these circuits, is studied. We refine relevant mathematical definitions of the hold-in and pull-in ranges related to the local and global stability. Stability analysis of the steady state for the charge-pump phase locked loop is non-trivial: straight-forward linearization of available CP-PLL models may lead to incorrect conclusions, because the system is not smooth near the steady state and may experience overload. In this work necessary details for local stability analysis are presented and the hold-in range is computed. An upper estimate of the pull-in range is obtained via the analysis of limit cycles. The study provided an answer to Gardner’s conjecture on the similarity of transient responses of CP-PLL and equivalent classical PLL and to conjectures on the infinite pull-in range of CP-PLL with proportionally-integrating filter. [ABSTRACT FROM AUTHOR]

Flash memory is an important component in many embedded system-on-a-chip applications, which drives the need to generate high write/erase voltages in generic CMOS processes. In this paper, we present a regulated, high-voltage charge pump for erasing Flash memory and floating-gate transistors. This 0.069-mm2 charge pump was fabricated in a 0.35 \mu \text m standard CMOS process. While operating from a 2.5 V supply, the charge pump generates regulated voltages up to 16 V with a PSRR of 52 dB and an output impedance of 6.8 \textk\Omega . To reduce power consumption for use in battery-powered applications, this charge pump uses a variable-frequency regulation technique and a new circuit for minimizing short-circuit current in the clock-generation circuitry; the resulting charge pump is able to erase the charge on floating-gate transistors using only $1.45 \mu J$ . [ABSTRACT FROM AUTHOR]

This paper presents a systematic methodology for the co-design of matching network and rectifier of radio frequency (RF) harvesters that results in maximum power conversion efficiency (PCE) for a given available power. This method is based on our newly developed rectifier model capable of calculating the CMOS Dickson’s rectifier’s input/output voltages at a given input power developed for low/high input power regimes. The proposed model allows for the co-design of the matching network and the rectifier in a fraction of time that takes for the design of the RF energy harvester using previously developed models relying on the knowledge of rectifier’s input voltage levels where a computationally extensive iterative design procedure must be performed because of the interdependence of the rectifier’s input voltage, the input power, and the matching network’s and rectifier’s parameters. The proposed methodology is capable of accurately predicting matching network components’ sizes for both the lossless and lossy matching networks for a maximum power transfer. Utilizing the proposed methodology, the designers can produce efficiency contour plots for a given input power for finding the optimum matching network and rectifier’s parameters for maximum PCE. The model, simulation, and measurement results for different parameters and input power levels in a 130-nm process are in good agreement. [ABSTRACT FROM AUTHOR]

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra-low-power level detector, and a boost converter. The energy harvesting system can generate an output voltage of 1 V and delivers a maximum power of $4.5~\mu \text{W}$ from a 60 mV supply. This system has been implemented in a standard $0.18~\mu \text{m}$ CMOS technology, uses neither zero-threshold voltage (normally-on) negative-channel metal-oxide semiconductor nor microelectromechanical systems switches and occupies 3.3 mm2. [ABSTRACT FROM AUTHOR]

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- \mu \textm CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients. [ABSTRACT FROM PUBLISHER]

Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches. [ABSTRACT FROM PUBLISHER]

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm2 and 0.0126 mm2, respectively. The system also contains an off-the-shelf 3.2 mm $\times2.5$ mm $\times0.9$ mm supercapacitor working as an off-chip battery or energy reservoir between the PMU and the voltage regulator. Experimental results show that the fast energy recovery of the on-chip solar cell and PMU permits the system to replenish the supercapacitor with enough charge as to sustain Bluetooth Low Energy (BLE) communications even with input light powers of 510 nW. The whole system is able to self-start-up without external mechanisms at 340 nW. This work is the first step towards a self-supplied sensor node with processing and communication capabilities. The small form factor and ultra-low power consumption of the system components is in compliance with biomedical applications requirements. [ABSTRACT FROM AUTHOR]

This paper presents an inductor-less switched capacitor based energy harvester, which can simultaneously harvest from 2 energy sources (Solar + Piezo). The proposed harvester employs maximum power point tracking algorithm, by changing the conversion ratios of the charge pumps for piezo and solar sources, and output voltage control by varying the switching frequency. The proposed MPPT algorithm can match the input impedance of two sources simultaneously. Implemented in 65nm CMOS, the proposed harvester can generate a fixed output between 1.8 and 2.5 V output while delivering 35 $\mu \text{W}$ to 70 $\mu \text{W}$ power with a peak power conversion efficiency of 74.6%. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

The design and analytical modeling of a high efficiency energy harvester comprising a passive voltage-boosting network (VBN) and a switching charge pump rectifier (CPR) is presented in this paper. To improve the power conversion efficiency (PCE), the VBN increases the voltage at the input of the CPR and provides control signals for switching. Unlike traditional Schottky and diode-connected MOS transistor rectifiers, the proposed orthogonally switching CPR (OS-CPR) comprises MOS transistors as voltage-controlled switches. Analytical models for the OS-CPR are developed and presented. Circuit-level optimization techniques are employed to reduce conduction and switching losses. Simulated in a 90 nm standard CMOS technology (IBM 9RF), a 5-stage 915 MHz OS-CPR achieves a dc voltage of 1.35 V and a PCE of 11.9% with a 1 M\Omega load at -18.2 dBm available input power (PS,AV). To show technology scalability of the design, the OS-CPR is also validated using AMS 0.18 \mum high-voltage (HV) CMOS technology. When benchmarked with traditional rectifiers, the OS-CPR (under similar conditions) achieves a higher PCE and a higher output dc voltage. The OS-CPR is easily scalable to operate over multiple sub-GHz ISM frequency bands. [ABSTRACT FROM PUBLISHER]

The charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory. [ABSTRACT FROM PUBLISHER]

Capacitive kinetic energy harvesters (KEH) employ conditioning circuits which achieve a dynamic biasing of the transducer's variable capacitor. This paper, composed of two articles Part 1 and Part 2, proposes a unified theory describing electrical and electromechanical properties of an important and wide class of conditioning circuits: those implementing a rectangular charge-voltage cycle. The article Part 1 introduces a basic configuration of conditioning circuit implementing an ideal rectangular QV cycle, and discusses its known practical implementations: the Roundy charge pump with different flyback mechanisms, and configurations based on the Bennet's doubler. In Part 1, the analysis is done in the electrical domain, without accounting for electromechanical coupling, while in Part 2, the full electromechanical system is analyzed. An optimization approach common to all configurations is proposed. A comparison is made between different topologies and operation modes, based on the maximal energy converted in one cycle under similar electrical and mechanical conditions. The last section discusses practical implementation of circuits with smart and adaptive behavior, and presents experimental results obtained with state-of-the art MEMS capacitive KEH devices. [ABSTRACT FROM PUBLISHER]

This paper presents two circuit topologies of battery-less integrated boost oscillators suitable for kick-starting electronic systems in fully discharged states with ultra-low input voltages, in the context of energy harvesting applications based on thermoelectric generators, by coupling a piezoelectric transformer in a feedback loop. With respect to the prior work, the first presented solution is a double polarity circuit designed in a 0.18~\mu \textm CMOS technology able to boost ultra-low positive and negative voltages without using switching matrixes. The circuit exploits a CMOS inverter made up of low threshold transistors, and also includes a hysteretic voltage monitor consuming only ~15 nW to enable an external circuit. The minimum achieved positive and negative oscillation voltages are +15 and −8 mV, which to the best of the authors’ knowledge, are among the lowest start-up voltages achieved in literature up to now without using magnetic components. Moreover, the input impedance in the range of several \textk\Omega makes the presented solution suitable also for high impedances sources, such as rectennas. The second presented circuit, designed in a 0.32~\mu \textm CMOS technology, exploits an input stage based on depletion-mode MOSFETs in a common source stage configuration and achieves a maximum step ratio of ~60. [ABSTRACT FROM AUTHOR]

Previous research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than -20~dBm. This paper presents a dual-channel 15-bit UHF passive CMOS RFID tag prototype that can work at sensitivity lower than -20~dBm. The proposed tag chip harvests energy and backscatters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) channel and receives downlink data at 433-MHz channel. Consequently, the downlink data transmission does not interrupt our tag from harvesting RF energy. To use the harvested energy efficiently, we design a tag chip that includes neither a regulator nor a VCO such that the harvested energy is completely used in receiving, processing, and backscattering data. Without a regulator, our tag uses as few active analog circuits as possible in the receiver front-end. Instead, our tag uses a novel digital circuit to decode the received data. Without a VCO, the design of our tag can extract the required clock signal from the downlink data. Measurement result shows that the sensitivity of the proposed passive tag chip can reach down to -21.2~dBm. Such result corresponds to a 19.6-m reader-to-tag distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The chip was fabricated in TSMC 0.18-\mum CMOS process. The die area is 0.958 mm \times 0.931mm. [ABSTRACT FROM AUTHOR]

In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a \Delta\Sigma ADC. The 0.13 \mum CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The CP based modulator realizes 87.8 dB SNDR, 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth with 148 \muW power consumption. The conventional ADC has similar performance but dissipates 241 \muW. The energy required per conversion-step for the CP based ADC (0.369 pJ/step) is almost 40% lower than that of the conventional ADC (0.607 pJ/step). [ABSTRACT FROM PUBLISHER]

This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10^-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm^2 and 0.94 mm^2, respectively, in a 0.13 \mum 1P8M CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply. [ABSTRACT FROM PUBLISHER]

Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22~dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18~\mum digital CMOS process, the prototype PLL occupies an area of 0.18~\mum and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively. [ABSTRACT FROM PUBLISHER]

Fractional-N phase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps (\Delta \Sigma-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable \Delta \Sigma-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter (\Delta \Sigma FDC) in place of a TDC to retain the benefits of TDC-PLLs and \Delta \Sigma-PLLs. This paper proposes a practical \Delta \Sigma FDC based PLL in which the quantization noise is equivalent to that of a \Delta \Sigma-PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the \Delta \Sigma FDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications. [ABSTRACT FROM PUBLISHER]

This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated with the ADC and, besides a low jitter clock reference, no other external high quality generators are required. The complete system comprises two synchronized phase-locked loops (PLLs), one based on a two-integrator oscillator capable of providing low distortion outputs and another based on a relaxation oscillator providing low jitter squared output, to allow coherent sampling. A detailed description of the building blocks of both PLLs is given as well as the techniques used to minimize area of the loop filters (LFs), to stabilize the output amplitude of the two-integrator oscillator to a known value, and to improve the total harmonic distortion (THD) of this oscillator. Post-layout simulations, in a 0.13 \mu\ m CMOS technology, of the proposed BIST scheme applied to a case-study 6-bit 1 GS/s ADC are shown and validate the proposed test methodology. [ABSTRACT FROM PUBLISHER]

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL. [ABSTRACT FROM PUBLISHER]

The main focus of this paper is the implementation of mixed-signal peak current mode control in low-power dc–dc converters for portable applications. A DAC is used to link the digital voltage loop compensator to the analog peak current mode loop. Conventional DAC architectures, such as flash or \Delta\Sigma are not suitable due to excessive power consumption and limited bandwidth of the reconstruction filter, respectively. The charge-pump based DAC (CP-DAC) used in this work has relatively poor linearity compared to more expensive DAC topologies; however, this can be tolerated since the linearity has a minor effect on the converter dynamics as long as the limit-cycle conditions are met. The CP-DAC has a guaranteed monotonic behavior from the digital current command to the peak inductor current, which is essential for maintaining stability. A buck converter IC, which was fabricated in a 0.18 \mu \m CMOS process with 5 V compatible transistors, achieves a response time of 4 \mu \s at fs=3\ \MHz and Vout=1\ \V, for a 200 mA load-step. The active area of the controller is only 0.077 \mm^2, and the total controller current-draw, which is heavily dominated by the on-chip senseFET current-sensor, is below 250 \mu \A for a load current of Iout=50\ \mA. [ABSTRACT FROM PUBLISHER]

Dedicated to neuron stimulation circuits, a stage-selective negative voltage generator is proposed to enhance the overall power efficiency. Since the supplied voltage of the stimulus driver is subject to applications and treatments, an extensive output requirement of supply is demanded to achieve energy-efficient stimulation. The charge pump is implemented as a negative voltage generator for on-chip design. In a limited area, excess power loss is eliminated by reconfiguring the cascaded architecture and clocks. Digitally programmable voltage levels can be outputted by varying the number of stages dynamically. The function of stage selection is achieved by the proposed stage-selective scheme. With appreciate control, the stage-selective negative voltage generator can maintain higher power efficiency under different output voltage levels and loading conditions. The technique improves 40% power conversion ratio at most but only leads to an increment of 8% in area occupation. The measured output voltage covers from −0.3 V to −9.3 V within a maximum 5.5-mA output current, which is verified in a 0.25- $\mu \text{m}$ BCD process. [ABSTRACT FROM AUTHOR]

A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to dynamically control the CTSs' gate, and the two branches utilize both NMOS and PMOS to implement their switching structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively improves pumping efficiency. The last stage is specially designed to improve the charge pump's charge and capacitance drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate under a low voltage supply. The proposed charge pump circuit is designed in a standard 0.18 \mum CMOS process. It consists of 6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 320 mV supply, the measured output voltage of the proposed charge pump can rise from 0 to 2.04 V within 0.1 milliseconds. [ABSTRACT FROM AUTHOR]

A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 \mum CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain (KVCO of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 \mus including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is -123 dBc/Hz and the integrated phase error (1 kHz–2 MHz) is 1.26^\circ. [ABSTRACT FROM PUBLISHER]

A new scheme of a gain/efficiency-improved serial- parallel switched-capacitor converter (SPSCC) is proposed by combining an adaptive-conversion-ratio (ACR) and pulse-width- modulation (PWM) control for step-up DC–DC conversion. For improving gain, the power part consists of one mc-stage cell and one nc-stage cell in cascade to obtain the step-up gain of (mc+1)\times(nc+1) at most. For improving efficiency, the ACR control with adapting stage number m,n is presented to select a proper gain of (m+1)\times(n+1) (m=1,2,\ldots,mc, n=1,2,\ldots,nc) according to the desired output. Further, the PWM control is adopted to enhance output regulation as well as robustness to source/loading variation. Some theoretical analysis and control design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a SPSCC prototype, and all results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM PUBLISHER]

A dual power supply ultra low-power 1 kbits EEPROM for passive UHF RFID is presented. The read power source is 1 V, while the write power source is 1.65 V, which is only activated in the write mode. To reduce the power of the read circuit without impacting the performance, a pre-charge scheme, a feedback scheme and a self-detect circuit, combined with a special read time sequence are adopted. A time-divided charge pump is proposed to reduce the current surge of the charge pump at the startup phase. The EEPROM IP has been fabricated in a SMIC 0.18~\mum 2P4M EEPROM process. The die size of the proposed EEPROM IP is 0.12~mm^2. The read and write currents of the EEPROM IP are 1.18~\muA and 33~\muA respectively. Under a 110^\circ temperature variation, the power variation of the read operation is 15%. The EEPROM IP is then verified in a full UHF RFID chip. Tested by a commercial reader at 4 W EIRP, the maximum read and write communication ranges are 6 m and 3 m respectively. The measured voltage drop of the output of rectifier Vrect caused by the current surge of the charge pump is smaller than 50 mV. [ABSTRACT FROM PUBLISHER]

A design methodology for an area-optimized integrated charge pump is described suitable for on-chip high-voltage reverse bias of single-photon avalanche diodes (SPADs). The high-voltage generation block is implemented in a general-purpose 0.13- $\mu \text{m}$ CMOS process and is capable of generating a maximum regulated output voltage of 17.7 V from an input of 1.8 V. An ON–OFF regulation scheme with dynamic charging and discharging capability of the charge pump provides fast recovery of the output bias voltage during SPAD transients, where overshoot and undershoot must both be corrected during active quench and reset. Following a SPAD avalanche current pulse, the measured transient recovery time is 500 ns from a 150-mV overshoot and a 500-mV undershoot to reach 99% of steady-state output. The implemented SPAD bias generation system occupies 0.175-mm2 chip area, without requiring an off-chip load capacitor. [ABSTRACT FROM AUTHOR]

A closed-loop multistage (n-stage) multiphase (p-phase) switched-capacitor boost dc–ac inverter (MPSCI) is proposed by combining a variable-phase control (VPC) and sinusoidal pulsewidth-modulation (SPWM) technique for low-power step-up inversion/regulation. Its power stage contains two parts: an MPSC booster (front) and an H-bridge (rear). An n-stage p-phase MPSC is for an inductor-less boost dc–dc conversion, where n voltage doublers are in series for boosting voltage gain up to 2^n at most. For improving efficiency, VPC is suggested to realize a variable multiphase operation by changing phase number p and topological path for more suitable gain level. An H-bridge is employed for dc–ac conversion, where four switches are controlled by SPWM not only for full-wave operation, but also for enhancing output regulation as well as robustness to source/loading variation. The analysis and design include an MPSCI model, steady-state/dynamic analysis, conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), filter, and control design. Finally, the closed-loop MPSCI is simulated, and the hardware is implemented and tested. All results are illustrated to show the efficacy of the proposed scheme. [ABSTRACT FROM PUBLISHER]

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order $\Delta \Sigma $ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement. [ABSTRACT FROM AUTHOR]

An active diode IC-based full-wave charge pump is presented. It interfaces to a vibration harvester designed for low acceleration non-periodic bridge vibrations. The charge pump’s unique architecture uses only two comparators to switch the charge pump’s eight stages. This architecture reduces power and allows for a novel passive diode switching technique that also enables a reduction in the turn-on voltage. This switching technique initially functions based only on the AC input without a DC supply. This architecture is used to enable cold start-up using the charge pump’s external 100~\mu \textF capacitors. These large capacitors create a stable power supply for start-up from one low voltage AC input based off of bridge vibrations that are random and infrequent. Its rectification circuitry is fabricated in 180 nm CMOS on a 1.2 mm2 die. The circuit inputs, generated using a shaker table, are periodic sine-waves or non-periodic mechanical frequency up-converted vibration harvester outputs. Measurements show that the diode drop reduction allows cold start-up and boosting to >1.5 V with low power ( \sim 8.5~\mu \textW ) non-periodic harvester outputs or 220 mV open circuit voltage periodic (~100 Hz) inputs. This IC demonstrates ~50% efficiency with an up-conversion-based harvester and \sim 1~\mu \textW active power dissipation. [ABSTRACT FROM PUBLISHER]

A high-speed dynamic biasing technique is presented for reducing op amp power in discrete-time, multistage, analog circuits employing op amp sharing. To exploit typical power scaling in such circuits, a charge pump, of which the on-times of up and down currents are controlled by two comparators, performs rapid change of the op amp bias condition between a low-current mode and a high-current mode during nonoverlapping clock periods of the two phase clocks. The errors caused by finite comparator delay are compensated for by embedding intentional offset voltages in the comparators, which are implemented by using asymmetric differential input pairs in the comparators. To verify the efficacy of the proposed biasing technique, an 11-b pipelined analog-to-digital converter (ADC) has been implemented using 0.15- \mu \textm devices in a 28-nm CMOS technology. With a 20-MHz sampling clock, the ADC achieves a 61.8-dB SNDR while consuming a 2.24-mW power from a 1.8-V supply. The MDAC and ADC power are reduced by about 45% and 30%, respectively, compared with a conventional pipelined ADC employing an op amp in each MDAC. Owing to the simple structure of the proposed dynamic biasing, the prototype ADC occupies only 0.052 mm2. [ABSTRACT FROM AUTHOR]

A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18- \mu \text m~1.8 -V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through using the proposed new clocking scheme. The voltage ripples in the power supply line, which is connected with the charge pump input, are also smoothed greatly as the filter circuit does. The proposed scheme is used to decrease the smoothing capacitance in the power line of charge pump for reducing the size of implantable devices in biomedical application. In addition, the power efficiency is improved. The proposed cross-couple charge pump can provide 10.5-V output voltage with 3.5-mA output current, and the power efficiency of the charge pump can be up to 69%. [ABSTRACT FROM AUTHOR]

A charge amplifier incorporates digital circuits as an alternative to the classic analog amplifier to achieve a high open-loop gain to maintain a consistent closed-loop gain over input capacitance variations. The digital-assisted charge amplifier employs a comparator, digital control logic, differential charge pump, current sources, common-mode feedback, and clock generator. A detailed analysis studies the amplifier stability and trade-off between ripple voltage and settling speed. A novel two-step reset scheme and tri-state charge pump minimize the output offset due to ripple residues. Fabricated in a 180-nm CMOS process, the digital-assisted amplifier achieves an open-loop gain of 101 dB, closed-loop gain of $15.0~\mu \text{V}$ /e-, input-referred noise of 221 $\text{e}^{-}$ rms, and output swing of 3 V while consuming 2.19 mW. The amplifier also demonstrates the ability to amplify a dynamic input current using a custom opto-electronic test setup. The amplifier maintains a consistent closed-loop gain across parasitic input capacitance from 6 pF to 94 pF. [ABSTRACT FROM AUTHOR]

Modeling and design aspects of on-chip photovoltaic energy conversion, voltage boosting and storage in bulk CMOS are investigated under the constraints of indoor illumination and small form factor. A power-supply architecture consisting of a photovoltaic converter, a clock generator, a charge-pump and a storage capacitor is considered. Maximization of the recharging rate of the capacitor at the low end of irradiance is adopted as the aim of design optimization. First, photodiodes available for conversion in bulk CMOS are comparatively evaluated, and potentially the most efficient ones are experimentally characterized for the typical range of indoor irradiance. Next, a generic model is developed and experimentally verified for a clock generator powered by a converter built with these photodiodes. This is followed by the modeling and experimental verification of a Dickson charge-pump whose single-device rectifier is free of body effect and near-ideal in forward characteristic. These models are based on the subthreshold operation of devices as necessitated by optimization under the limitations of bulk-CMOS stacking and indoor irradiance. Guidelines for design optimization are derived from these models. Experimental work is based on two test chips fabricated in 0.18-\mu\ m bulk CMOS with deep n-well option. [ABSTRACT FROM AUTHOR]

An interleaved scheme of variable-conversion-ratio (VCR) multistage switched-capacitor-voltage-multiplier/divider (SCVM/SCVD) converter is proposed by combining a VCR-based phase generator and pulse-width-modulation (PWM) controller to integrate step-up and down modes in one structure for high-efficiency conversion. The power part consists of two mc-stage SC cells (front) and two nc-stage SC cells (rear) in series for step-up/down gain of mc\times nc or 1/(mc\times nc) at most. Here, VCR-based phase generator is suggested with changing the running stage number m,n and topological path to obtain a suitable gain of m\times n or 1/(m\times n) (m=1,2,\ldots,mc, n=1,2,\ldots,nc) for improving efficiency, especially for the lower desired output. Besides, PWM is adopted to enhance output regulation as well as robustness to source/loading variation. Further, some theoretical analysis and design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed-loop SCVM/SCVD is simulated, and the hardware is implemented and tested. All results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM PUBLISHER]

A 1.5–1.6 GHz dual-loop phase-locked loop in 0.18-\mu\ m CMOS locks in 40 \mu\ s and draws only 26 mA from 1.8 V . The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1^\circ and the phase noise spectral density is - \ 116.8~\ dBc/\ Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are - \ 83~\ dBc and - \ 105~\ dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively. [ABSTRACT FROM PUBLISHER]

As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumed. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single-event upsets (SEU), which are known to affect DSM circuits working under low voltages. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. [ABSTRACT FROM AUTHOR]

Randomizing the positions of charge pump current pulses in a PLL breaks their periodicity and redistributes the reference spurs into broadband noise. Closed form expressions for the power spectral density (PSD) of pulse position modulated (PPM) signals are derived and intuitive explanations for the results are given. The redistributed noise has a high-pass shape and does not affect the close in phase noise of the PLL. PPM using a uniformly distributed i.i.d. sequence completely removes the spurs and provides a first-order shaping of redistributed noise. Higher order shaping and reduction of redistributed noise at intermediate offset frequencies are possible using PPM with a high-pass shaped modulating sequence and pulse repetition. Circuit implementations of these techniques are given and their nonidealities are discussed. Simulation results from a 1 GHz PLL operating from a reference frequency of 20 MHz and a bandwidth of 1 MHz confirm the results of the analysis and viability of the proposed techniques. In the presence of nonidealities spurs can be reduced by at least 13 dB without any trimming of the delays in the PPM circuits and by 25 dB after trimming the delays to within 5% of the nominal value. [ABSTRACT FROM PUBLISHER]