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For a class of nontriangular nonlinear systems in presence of unknown disturbances, we propose a predictor-based neural dynamic surface control (PNDSC) strategy in this paper. This nontriangular system is transformed via the mean value theorem, and a predictor is then constructed. To avoid an algebraic loop problem, partial state vectors are employed as input signals of neural networks (NNs) for approximating unknown dynamics, and compensation items are designed to compensate for approximation errors from NNs. Different from the traditional NDSC, the PNDSC in this paper utilizes prediction errors to update learning parameters for improving NNs’ learning behaviors with overlarge adaptive gains. On the basis of improved NNs’ approximation behaviors, a predictor-based NNs disturbance observer (PNNDO) is constructed for compensation for external disturbances and approximation errors from NNs. Furthermore, with predictors, a normalization method of weights is developed to reduce the number of online learning parameters. On the basis of the aforementioned result, measurement noises are taken into account in our predictor-based neural control strategy. We employ predictor states, rather than measurement information paralyzed by noises, in design of our control strategy. This reduces high-frequency oscillations in control input. A Lyapunov-based stability analysis shows that all signals are ultimately bounded in the closed-loop system. Finally, the effectiveness of the proposed control strategy is verified by a numerical example and a permanent magnet brushless DC motor system. [ABSTRACT FROM AUTHOR]

Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of $m$ contiguous bits (a segment of $m$ bits) is extracted from each of the two $n$ -bits operand, the two segments are in input to a small $m\times m$ internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications. [ABSTRACT FROM AUTHOR]

This paper studies an $H_{\infty }$ model reduction problem for interval frequency negative imaginary (IFNI) systems. For a given IFNI system, our goal is to find a reduced-order IFNI system satisfying a pre-specified $H_{\infty }$ approximation error bound over the finite-frequency interval. Necessary and sufficient conditions in terms of matrix inequalities are derived for the existence and construction of an $H_{\infty }$ reduced-order IFNI system. An improved iterative algorithm is provided to solve the matrix inequalities and to minimize the $H_{\infty }$ approximation error. The proposed method is further clarified via the application to the electrical circuits, such as high-order Sallen–Key low-pass filter, piezoelectric tube scanner, and RLC circuit. The simulation results on these electrical circuits are compared with the finite-frequency interval Gramians-based model reduction method both in the frequency domain and time domain. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique based on the current steering technique for the generation of a reconfigurable current that approximates the linear, squaring, cubic, and exponential and their descending analog functions. The proposed implementation can be easily programmed to generate these functions by simply reconfiguring the weighting factors of current sources and offers an extendable input voltage range keeping excellent accuracy. The circuit topology has been fabricated using $0.18~\mu \text{m}$ TSMC CMOS process under 1.8 V supply voltage. Measurements results validate the theoretical analysis giving for 400 mV input voltage range while keeping small relative approximation errors, 0.3%, 1%, 1.9%, and 0.7% for linear, squaring, cubic, and exponential, respectively. [ABSTRACT FROM AUTHOR]

This paper considers two-rate based structures for variable fractional-delay (VFD) finite-length impulse response (FIR) filters. They are single-rate structures but derived through a two-rate approach. The basic structure considered hitherto utilizes a regular half-band (HB) linear-phase filter and the Farrow structure with linear-phase subfilters. Especially for wide-band specifications, this structure is computationally efficient because most of the overall arithmetic complexity is due to the HB filter which is common to all Farrow-structure subfilters. This paper extends and generalizes existing results. Firstly, frequency-response masking (FRM) HB filters are utilized which offer further complexity reductions. Secondly, both linear-phase and low-delay subfilters are treated and combined which offers trade-offs between the complexity, delay, and magnitude response overshoot which is typical for low-delay filters. Thirdly, the HB filter is replaced by a general filter which enables additional frequency-response constraints in the upper frequency band which normally is treated as a don't-care band. Wide-band design examples (90, 95, and 98% of the Nyquist band) reveal arithmetic complexity savings between some 20 and 85% compared with other structures, including infinite-length impulse response structures. Hence, the VFD filter structures proposed in this paper exhibit the lowest arithmetic complexity among all hitherto published VFD filter structures. [ABSTRACT FROM AUTHOR]

In this paper, an exchange algorithm is proposed to design sparse linear phase finite impulse response (FIR) filters with reduced effective length. The sparse FIR filter design problem is formally an ${l} _{0}$ -norm minimization problem. This original design problem is re-formulated by encoding the filter coefficients using a binary encoding vector, which represents the locations of the zero and non-zero filter coefficients. An iterative 0-1 exchange process with proper direction control is proposed to propel the minimax approximation error toward the specified upper bound of error for sparsity maximization. The effective length is optimized with a lower priority than sparsity in the proposed algorithm. Simulation results show that the proposed algorithm is superior to the existing algorithms in terms of both sparsity and/or effective length in most cases. [ABSTRACT FROM AUTHOR]

This paper presents an approximate closed-form transfer function model for diverse differential interconnects. The proposed model is simple, intuitive, and can accurately describe various interconnects satisfying the validity conditions which theoretically bound the approximation error. The proposed model also provides a conceptual circuit representation by analogy with an equivalent circuit model of a single-ended interconnect. The model's accuracy is verified by comparing calculated through- and crosstalk-transfer functions against w-element SPICE simulation results for various LC-dominant and RC-dominant interconnects. Our analysis also empirically verifies that the approximation error is bounded by the validity parameters. In addition, the computation time is improved by about 157 times compared to that of the previous numerical computation method built-in SPICE simulator. With the proposed channel model, designers can easily understand and analyze the behaviors of various differential interconnects without complex analysis. [ABSTRACT FROM AUTHOR]

In this paper, a cascaded form sparse finite impulse response (FIR) filter design algorithm is proposed. By decomposing a filter into two subfilters, the sparse filter design problem is reformulated as a quadratic constrained ${l} _{0}$ -norm minimization problem, which is further transformed to a convex problem through the introduction of a binary masking vector. An iterative forth-and-back search with sequence direction and error direction control is proposed to optimize the binary masking vector by minimizing the distance between the minimax approximation error and the specified upper bound. Experimental results show that the proposed design algorithm can improve the sparsity with comparable or even lower effective filter order. [ABSTRACT FROM AUTHOR]

This paper presents a novel design methodology to turn the timing violation caused by aging into computation approximation error without the reliability guardband or increasing the supply voltage. It can be realized by accurately monitoring the critical path delay at run-time. We evaluate the proposal at two levels: RTL component level and system level. The experimental results at the RTL component level show a significant improvement in terms of (normalized) mean squared error caused by timing violation, and those at the system level show that the proposed approach successfully transforms the aging-induced timing violation errors into much less harmful computation approximation errors, and thus it recovers image quality up to perceptually acceptable levels. It reduces the dynamic and static power consumptions by 21.45% and 10.78%, respectively, with 0.8% area overhead compared to the conventional approach. [ABSTRACT FROM AUTHOR]

Transcendental functions are commonly used in many fields such as nonlinear functions of artificial neural networks (ANNs). Due to nonlinearity of these functions, hardware implementation of the functions faces many challenges. Some methods cannot control the approximation accuracy beforehand, or they cannot approximate target functions accurately and efficiently. Other methods can only approximate a particular function without generality. A universal piecewise linear (PWL) approximation method is proposed to solve the problems existing in the above methods. In this paper, a general piecewise linear (PWL) approximation method with controllable maximum absolute error for transcend-ental functions is proposed. The method has the self-adaptive capability to choose the smallest number of segments under the constraint of a controllable maximum absolute error. Therefore, it requires fewer segments and incurs less hardware overhead. Moreover, it can approximate any transcendental functions and does not rely on any properties of the target function. Comparing our work with other methods used in three transcendental functions, including the sigmoid, hyperbolic tangent, and logarithmic function, our method improves the approximation accuracy by 4.5 times, 2.1 times, and 1.3 times, respectively; in addition, our method is more efficient and it reduces the circuit area by 49.9%, 22.4%, and 28.5%, respectively. [ABSTRACT FROM AUTHOR]

This paper analyzes the spurs due to delay line (DL) buffer mismatch errors and phase quantization errors in a digital-to-time conversion (DTC) direct frequency synthesizer. Applying the time/frequency axis scaling property of the Discrete Fourier Transform (DFT) to a close approximation of the general case of both buffer error and quantization error spurs, it is shown that the spur spectra for all possible output frequencies can be divided into a very small number of classes. All the spectra within a class are scaled and systematically re-arranged versions of each other. For a DTC with a phase accumulator with I integer and M fractional bits, this result simplifies the number of spectra from 2^(I+M) to M. The condition that allows separation of the buffer errors spur locations from the quantization error spur location is derived. Spurs predicted based on the analysis match closely with actual measurements performed on a 90 nm CMOS DTC synthesizer. The spur analysis also applies to the flying adder (FA) synthesizer. [ABSTRACT FROM PUBLISHER]

This paper introduces a class of wide-band linear-phase finite-length impulse response (FIR) differentiators. It is based on two-rate and frequency-response masking techniques. It is shown how to use these techniques to obtain all four types of linear-phase FIR differentiators. Design examples demonstrate that differentiators in this class can achieve substantial savings in arithmetic complexity in comparison with conventional direct-form linear-phase FIR differentiators. The savings achievable depend on the bandwidth and increase with increasing bandwidth beyond the break-even points which are in the neighborhood of 90% (80%) of the whole bandwidth for Type II and III (Type I and IV) differentiators. The price to pay for the savings is a moderate increase in the delay and number of delay elements. Further, in terms of structural arithmetic operations, the proposed filters are comparable to filters based on piecewise-polynomial impulse responses. The advantage of the proposed filters is that they can be implemented using non-recursive structures as opposed to the polynomial-based filters which are implemented with recursive structures. [ABSTRACT FROM PUBLISHER]

In this paper, we propose model reduction algorithms based on the frequency-domain interval Gramians for 1-D and separable denominator 2-D discrete-time systems using balanced truncation as a parameterized combination of unweighted and the limited-frequency interval Gramians. The values of free parameters are computed using a line search optimization. The proposed algorithms provide a substantial improvement in the approximation error than the well-known existing techniques and generate stable reduced models along with an easily computable error-bound. The effectiveness of proposed algorithms is validated with the help of numerical examples of a sixth-order elliptic low-pass filter and a (6, 6)-order Roesser model of a separable denominator 2-D system. [ABSTRACT FROM AUTHOR]

Piecewise polynomial interpolation is a well-established technique for hardware function evaluation. The paper describes a novel technique to minimize polynomial coefficients wordlength with the aim of obtaining either exact or faithful rounding at a reduced hardware cost. The standard approaches employed in literature subdivide the design of piecewise-polynomial interpolators into three steps (coefficients calculation, coefficients quantization and arithmetic hardware optimization) and estimate conservatively the overall approximation error as the sum of the error components arising in each step. The proposed technique, using Integer Linear Programming (ILP), optimizes the polynomial coefficients taking into account all error components simultaneously. This gives two advantages. Firstly, we can obtain exactly rounded approximations; secondly, for faithfully rounded interpolators, we avoid any overdesign due to pessimistic assumptions on error components, optimizing in this way the resulting hardware. The proposed ILP based algorithm requires an acceptable CPU time (from few seconds to tens of minutes) and is suited for approximations up to, maximum, 24 input bits. The results compare favorably with previously published data. We present synthesis results in 28 nm and 90 nm CMOS technologies, to further assess the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

Fixed-width multipliers have two n-bits operands and produce an approximate n-bits results for their product. These multipliers discard part of the partial products matrix, to reduce hardware cost, and employ extra correction functions to reduce approximation error. [ABSTRACT FROM PUBLISHER]

Inverse-system approximation using finite-impulse responses (FIR) is essential to a broad area of signal-processing applications. The conventional Wiener filtering techniques based on the least-square approach cannot provide an analytical frame- work simultaneously governing two crucial problems, namely, the selection of model order and the evaluation of asymptotical error bounds. In fact, the square approximation error induced from the FIR realization of a linear time-invariant system is quite complicated, specifically for those system transfer functions pos- sessing repeated zeros with large multiplicities. Therefore, in this paper, we establish an isomorphism to characterize the z-trans- form pairs. In this mathematical paradigm, we will elaborate the problem of approximating an inverse system or filter with an infinite number of coefficients by an FIR filter and derive the new L1 and L2 approximation-error bounds between the actual inverse filter and the corresponding approximated FIR. Our new theories, analysis, and bounds can be utilized to quantify the appropriate model order for the inverse-system approximation that is often needed for signal processing, control, communications, etc. [ABSTRACT FROM AUTHOR]