Search

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

The series-paralleling technique of dc-dc converters is utilized in various domains of electrical engineering for improved power conversion. Previous studies have proposed and classified the control schemes for the series-paralleled converters. However, they have several restrictions and lack diversity. The purpose of this paper is to propose passivity-based control (PBC) for the diverse output series-parallel connection of dc-dc converters. It is proved that the output series-paralleled converters regulated by PBC are asymptotically stable. The output series-paralleled converters are numerically simulated to confirm the asymptotic stability. PBC is shown to maintain the stability of the output series-paralleled converters with diverse circuit topologies, parameters, and steady-states. The result of this paper theoretically supports the numerical and experimental considerations in the previous studies and justifies the further extension of the series-parallel connection. [ABSTRACT FROM AUTHOR]

An energy-harvesting interface that incorporates a continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) dc-dc converter with maximum power point tracking (MPPT) is introduced in this paper. By exploiting unique characteristics of a CSCR SC converter, an MPPT based on the hill climbing algorithm is implemented with a real-time power monitoring scheme with a frequency-mapped sampling capacitor DAC, allowing variation-tolerant MPPT for various types of energy sources. The harvestable voltage range is significantly extended by a step-up/down convertible CSCR SC converter, and the voltage conversion efficiency is further improved with matrix-structured and load-mapped power switches. With the test chip fabricated in 28nm FDSOI technology, the proposed energy harvesting interface shows peak conversion efficiency of 89% and average efficiency of > 80% for 60-2, $794~\mu \text{W}$. MPPT efficiency of > 97 % is confirmed with energy harvesting measurement with a solar cell. [ABSTRACT FROM AUTHOR]

Three types of bifurcations (instabilities) in the DC-DC converter under valley current mode control (VCMC) are analyzed, which is an extension of a recent paper on the peak current mode control (PCMC). The three bifurcations are border-collision, period-doubling, and saddle-node bifurcations. The corresponding critical (instability) conditions are derived. The derived conditions divide the parameter space into different operating modes. Contrary to the general belief that the critical conditions for VCMC and PCMC are symmetric with respect to the duty cycle D=1/2, most critical conditions are actually asymmetric. The dynamics symmetry is converter, bifurcation, loading, and parameter dependent, verified by bifurcation diagrams and time-domain simulations. The VCMC boost converter has rich dynamics and it is extensively analyzed. [ABSTRACT FROM AUTHOR]

This paper presents an iterative decimation approach to significantly alleviate the computational burden of centralized controllers applying real-time recursive system identification algorithms in multi-rail power converters. The proposed approach uses an adaptive update rate as opposed to the fixed update rate used in conventional adaptive filters. Also, the step size/forgetting factors vary at different iteration stages. As a result, a reduced computational burden and faster model update can be achieved. Besides, recursive algorithms, such as Recursive Least Square (RLS), Fast Affine Projection (FAP) and Kalman Filter (KF), contain two important updates per iteration cycle; Covariance Matrix Approximation (CMA) update and Gradient Vector (GV) update. Usually, the CMA update requires the greater computational effort than the GV update. Therefore, in circumstances where the sampled data in the regressor does not experience significant fluctuations, re-using the CMA, calculated from the last iteration cycle for the current update can result in computational cost savings for real-time system identification. In this paper, both iteration rate adjustment and CMA re-cycling are combined and applied to simultaneously identify the power converter models in a three-rail power conversion architecture. [ABSTRACT FROM AUTHOR]

The DC-DC converter severs as one of the crucial components in DC microgrid applications. In this paper, a novel low frequency current-mode control strategy is proposed to improve overshoot suppression performance for the boost converter against load current and source voltage disturbances. The control strategy is presented as a cascade dual-loop structure composed of a dynamic current-loop controller with asymmetric saturation and a PI form voltage-loop controller. With the low frequency information of disturbances, the designed dynamic current-loop controller delivers not only promising disturbance suppression but also superior reference current tracking. Simulation and experiment results are provided to illustrate the superiority of the proposed strategy on overshoot suppression. [ABSTRACT FROM AUTHOR]

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

Design details and analysis of the properties of a hysteresis switching controller for the Ćuk converter are provided in this paper. The design is based on a switching control law which minimizes a common Lyapunov function derivative for the converter's continuous modes of operation. These continuous modes of operation are both marginally stable which causes some particularities in the design procedure. The design also meets the specifications in terms of the converter's duty ratio and the frequency limitations. The proposed hysteresis controller performance is analyzed with respect to the operating modes of the converter and illustrated with a number of representative and relevant simulations. [ABSTRACT FROM PUBLISHER]

In this paper, four control strategies for DC-DC buck converters are proposed, compared and analyzed: a single-loop adaptive control strategy (SA), a double-loop adaptive control strategy (DA), a single-loop disturbance observer-based control strategy (SDOB) and a double-loop disturbance observer-based control strategy (DDOB). First, the nominal system without considering the parametric uncertainties of the DC-DC buck converter is built to help develop the SA and DA. The SA is built by adaptive and backstepping control approaches, and the DA is set up by adaptive and sliding mode control approaches. Additionally, a model considering parametric uncertainties is introduced, giving the opportunity to develop the SDOB and DDOB. The SDOB is developed using a designed disturbance observer and backstepping control technique, and the DDOB is synthesized using a designed disturbance observer and sliding mode control method. Finally, the advantages and disadvantages of the four proposed control strategies are compared and analyzed through experiments. [ABSTRACT FROM AUTHOR]

The growth of IoT applications requires DC-DC converters to have small printed circuit board (PCB) areas and high efficiency over a wide load range. A multi-mode operation of DC-DC converters, therefore, is often necessary to achieve this high efficiency over a wide load range. This paper introduces a tri-mode DC-DC buck converter for IoT applications. The tri-mode operation with PWM, PFM, and multiple-sawtooth PWM (MSPWM) modes helps to retain the high efficiency over the wide load range. The MSPWM mode also enhances a noise margin of the converter, ensuring a regular switching operation at an ultra-light load condition. With a load current prediction scheme, the proposed tri-mode converter requires neither additional load current sensor nor multiple mode controllers. In addition, a soft-start operation is employed to prevent an in-rush current. The proposed tri-mode buck converter has been fabricated through a 0.18- $\mu \text{m}$ CMOS process with a chip area of 0.97 mm $\times0.88$ mm. A load-dependent seamless mode transition is realized, and a maximum converter efficiency of 91% has been measured with a 7.4-MHz switching frequency. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated galvanically isolated dc–dc converter with data communication. The converter, which is fabricated in a 0.35- \mu \textm BCD technology, is made up of only two silicon dice and adopts two 6-kV on-chip transformers. It takes advantage of a customized architecture, which uses the isolated power control link to transfer bidirectional half-duplex data, thus reducing the overall silicon area and package size. The proposed dc–dc converter delivers up to 93-mW output power with 19% maximum power efficiency and an output voltage ranging from 2.4 V to 3.3 V, while achieving a data rate up to 50 Mb/s. [ABSTRACT FROM AUTHOR]

This paper presents a sliding mode dynamic output feedback controller design for Markovian jump systems under a communication network. For the inaccessible states and uncertain parts of Markovian jump systems, a novel integral-type sliding mode output feedback controller combined with system states and dynamic controller states is proposed. An event-triggered mechanism is introduced to reduce network bandwidth and resources requirements. The augmented dynamic system and complete control framework are presented together. The reachability of the novel integral-type sliding mode is proved. Then, based on delay-dependent Lyapunov functions, free-weighting matrices, and a singular value decomposition approach, a less conservative sufficient condition is proposed to ensure exponential stability with a weighted $\mathcal {L}_{2}$ - $\mathcal{ L}_{\infty}$ disturbance performance. Finally, a numerical and a DC-DC switched boost converter circuit simulations that verify the feasibility and effectiveness of the proposed controller are presented. [ABSTRACT FROM AUTHOR]

The performance of the inverse class-E power amplifier at sub-nominal condition for any duty ratio is investigated in this paper. Comparing with the inverse class-E power amplifier at nominal condition, which demands both zero-current-switching (ZCS) and zero-current-derivative-switching (ZCDS) conditions simultaneously, the presented inverse class-E power amplifier at sub-nominal condition is only restricted by the ZCS condition. The proposed power amplifier increases two design parameters because the ZCDS condition limitation is cancelled and the duty ratio can be arbitrarily set. The analytical results demonstrate that the theoretical drain efficiency is still 100% and that all the circuit elements can be adjusted by the two released parameters. Furthermore, the influences of the transistor's parasitic switch-on resistor and output capacitor are investigated and a simulation example is given to verify the proposed design methodology's accuracy. Although it is not sufficiently tolerant of the elements mismatches and the transistor's parasitic capacitor in practical design, the inverse class-E power amplifier at sub-nominal condition is still one of the promising candidates for high-efficiency power amplifier design if the two drawbacks are appropriately averted. [ABSTRACT FROM AUTHOR]

In this paper, hybrid dynamical systems theory is applied to the analysis and control of switched converters with Pulse-Width Modulated (PWM) inputs. The system is described by a state-space model with continuous flows and discrete jumps, without averaged equations. The modulation effects are captured in full without using time-dependent signals, by enlarging the state vector to include the PWM waveform generation process. Furthermore, the sample-and-hold mechanism associated with the sampling frequency is also taken into account with this approach. A control law is proposed based on a Lyapunov function candidate. Furthermore, convergence sets and the steady state jitter, inherent to PWM-based controllers, are analyzed estimating limit sets for the augmented state. Consequently, output chattering can be bounded. By using hybrid dynamical system theory, the control designer gains a deeper understanding of the effect of modulation in the closed-loop dynamics, avoiding the problems associated with the use averaged models. Experimental results validate the proposed method. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

Chain-link modular multilevel direct dc-dc converters (CLMMCs) have attracted much interest recently in for dc power systems because they achieve higher device utilization, lower power losses and they are physically more compact than the alternative front-to-front modular multilevel dc-ac-dc converters (FFMMCs). The CLMMCs rely on circulating an internal ac current to manage energy balance of the sub-module (SM) stacks but this current inevitably contributes to extra current stresses for circuit components and can also lead to excess reactive power circulation within the converter. This paper presents a circuit analysis that there exists a frequency value for the internal ac components that may minimize the current stresses and avoid excessive reactive power circulation. For illustration, the circuit analysis is applied to one of the base formats, the buck-boost CLMMC as an example. The key relationship between the CLMMC and the standard dc-ac modular multilevel converter is explored and established. The equivalent circuits for their dc and ac components with consideration of SM capacitance and SM voltage ripples are created and analyzed in detail, and a full derivation is provided for the specific ac frequency. From this example, this analytical method is extended and applied to other base formats of CLMMCs. The theoretical analysis and results are verified by a set of full-scale simulation examples and down-scaled experiments on a laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents a galvanically isolated dc-dc converter with multi-channel communication exploiting a single isolation transformer. The proposed architecture makes compliant both regulated output power and data transmission on the same isolation physical link by using ASK modulation of the power signal and data/control signal multiplexing. The dc-dc converter consists of two integrated chips fabricated in 0.18- $\mu \text{m}$ BCD and 0.13- $\mu \text{m}$ CMOS technologies, respectively, along with a thick polyimide transformer chip able to comply with reinforced isolation requirements. The dc-dc converter delivers an isolated output power up to 50 mW at 3.3-V output voltage, while providing three data channels with a data rate up to 10 Mb/s. [ABSTRACT FROM AUTHOR]

In this paper, a piecewise quadratic slope compensation technique for eliminating subharmonic oscillations in dc-dc switching converters is studied. With this technique, a self-generated signal is used in the compensation scheme resulting in a naturally full duty cycle stability domain. The expression of the piecewise quadratic compensating signal within a switching cycle is derived. It is obtained that the steady-state value of the amplitude of this signal is the same as in the conventional linear slope compensation scheme that guarantees stability for all values of the duty cycle. However, in the piecewise quadratic scheme this is achieved without exact knowledge of the inductance value nor sensing the input and the output voltages. The stability of the converter under the considered compensation scheme is also guaranteed for all values of the duty cycle with voltage loop open. A boost converter under peak current mode control is used to validate the theoretical results both by numerical simulations and by experiments. Simulation results are analyzed and compared to the performances of the state-of-art techniques with voltage loop closed. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

In this paper, we consider the modeling and (robust) control of a DC-DC Boost converter. In particular, we derive a mathematical model consisting of a constrained switched differential inclusion that includes all possible modes of operation of the converter. The obtained model is carefully selected to be amenable for the study of various important robustness properties. For this model, we design a control algorithm that induces robust, global asymptotic stability of a desired output voltage value. The guaranteed robustness properties ensure proper operation of the converter in the presence of noise in the state, unmodeled dynamics, and spatial regularization to reduce the high rate of switching. The establishment of these properties is enabled by recent tools for the study of robust stability in hybrid systems. Simulations illustrating the main results are included. [ABSTRACT FROM AUTHOR]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical equations describing the dynamic behavior. Numerical simulations from a detailed switched model validate the theoretical results and a good agreement is obtained. A boost converter prototype is built to validate the theoretical finding and the numerical simulations. It is observed that even when the analysis and the simulation predict zero inrush current, the experimental circuit still exhibits an unsuitable initial current peak and an unacceptable transient response during start-up. This phenomenon is mainly attributed to the presence of an unavoidable delay due to the computation time required by the digital control platform. The resulting inrush current is more pronounced in the presence of nonlinear load such as a CPL and saturable inductor. Some solutions are proposed to mitigate the inrush current problems. Simulations results taking into account the delay and experimental measurements demonstrate the validity of the proposed solutions. [ABSTRACT FROM AUTHOR]

This paper presents an inductor-less switched capacitor based energy harvester, which can simultaneously harvest from 2 energy sources (Solar + Piezo). The proposed harvester employs maximum power point tracking algorithm, by changing the conversion ratios of the charge pumps for piezo and solar sources, and output voltage control by varying the switching frequency. The proposed MPPT algorithm can match the input impedance of two sources simultaneously. Implemented in 65nm CMOS, the proposed harvester can generate a fixed output between 1.8 and 2.5 V output while delivering 35 $\mu \text{W}$ to 70 $\mu \text{W}$ power with a peak power conversion efficiency of 74.6%. [ABSTRACT FROM AUTHOR]

This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

The trend in next-generation switched-mode power supplies will lead to modular, scalable solutions which deliver power efficiently over a wide range of operation. This paper details a new approach to introduce more advanced control features like phase-alignment and frequency synchronization into such scalable solutions. While these methods have been incorporated into multi-phase converters in the past, they all require the distribution of information among the individual converters. In distributed solutions, dedicated communication signals have been used to share this information. An advantage of the proposed method is that it does not require such communication signals between the individual power supplies and is therefore fully scalable and cost effective. Perturbances generated by the switching actions of the individual converters on the common input/output voltage are used by each converter to harvest information about the switching actions of its counterparts. An algorithm is proposed to align the individual phases and synchronize the switching frequencies based on this information. This allows a reduction of input/output capacitor ripple currents, similar to techniques used in multi-phase designs. Experimental results for an FPGA prototype implementation are presented. [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

This paper presents a new free-running-oscillation resonant dc-dc converter with the Class-E oscillator and the Class-E rectifier, along with its design procedure and design curves for any conditions. The proposed converter is a free-running-oscillation system and has no gate-drive circuit to drive the MOSFET. There- fore, the structure of the proposed converter is simpler than that of class E² dc-dc converter. The proposed converter is suitable for a constant voltage and constant power operation under the fixed designed condition. The proposed converter has the ability to achieve a high power-conversion efficiency and low noises under high-frequency operation because of Class-E switching at both the oscillator and the rectifier. We investigate operations of the proposed converter by circuit experiments and show the validity of the design curves. This paper denotes two experimental results. One achieves 79.3% power-conversion efficiency under 1.54-W output power at an operating frequency 2.00 MHz. The other does 80.5% under 1.60-W output power at an operating frequency 1.98 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a sliding-mode control design of a boost-buck switching converter for a voltage step-up dc-ac conversion without the use of any transformer. This approach combines the step-up/step-down conversion ratio capability of the converter with the robustness properties of sliding-mode control. The proposed control strategy is based on the design of two sliding-control laws, one ensuring the control of a full-bridge buck converter for proper dc-ac conversion, and the other one the control a boost converter for guaranteeing a global dc-to-ac voltage step-up ratio. A set of design criteria and a complete design procedure of the sliding-control laws are derived from small-signal analysis and large-signal considerations. The experimental results presented in the paper evidence both the achievement of step-up dc-ac conversion with good accuracy and robustness in front of input voltage and load perturbations, thus validating the proposed approach. [ABSTRACT FROM AUTHOR]

This paper presents a design procedure of high-frequency loosely inductive coupled wireless power transfer (LIC-WPT) system based on class-E^2 dc-dc converter, taking into account the power loss reduction of inverter, coupling part, and rectifier simultaneously. Analytical expressions including the dc-to-dc efficiency of the WPT system are derived and the efficiency deterioration mechanism is explained by the circuit model. Through the analytical expressions, the design procedure for satisfying both the class-E switching conditions and power loss reductions at the coupling part is proposed from the circuit-theory viewpoint. The class-E^2 WPT system designed by the proposed design procedure achieves high dc-to-dc efficiency at low coupling coefficient, in particular, compared with those designed by the previous design strategies. The validity and effectiveness of the proposed design procedure were confirmed by PSpice simulations and circuit experiments. [ABSTRACT FROM PUBLISHER]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

This paper presents a 100 mV input, 500 mV output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 \mum CMOS technology for thermoelectric energy harvesting. The proposed AGB technique and near-threshold voltage (near-VTH) energy redistribution control (ERC) ensure high conversion efficiency over a wide range of load currents. The proposed method automatically reduces conduction and switching losses of power MOSFETs without the need for auxiliary power converters or additional off-chip inductors. The AGB technique reduces conduction and switching losses under heavy-load and light-load conditions, respectively. The experimental results show that the efficiency of the proposed converter is enhanced by 25.5% and 18% at output load currents of 1500 \muA and 50 \muA, respectively. The proposed step-up dc-dc converter achieves the lowest output voltage and provides the highest conversion efficiency of 83.4% to date in standard CMOS process for thermoelectric energy harvesting. [ABSTRACT FROM AUTHOR]

With reference to 48-V systems, used in electric and hybrid vehicles and for telecom and networking power supply, this paper presents the circuit/transistor-level design, implementation, and test of an inductorless dc/dc converter. Its architecture is a cascade of three switched-capacitor converters with step-up/down capabilities plus linear converters, working in parallel at the end of the cascade. It provides multiple regulated voltages, which are isolated from input failures. The design also includes on-chip control unit and a serial interface toward an external host. Experimental tests carried out on the chip, fabricated in 0.35- \mu \textm CMOS technology, proves that the design is suitable to face harsh operating environments, including the 48-V automotive one. Compared with the state-of-art, the proposed design stands for its wide input voltage regulation range, load/line regulation, power supply rejection ratio, and low electromagnetic interference emissions. [ABSTRACT FROM PUBLISHER]

A soft-switching bidirectional dc-dc converter using a lossless active snubber is proposed in this paper. In the proposed converter, zero-voltage-switching (ZVS) of main switches is achieved by utilizing an active snubber which consists of auxiliary switches, diodes, an inductor, and a capacitor. Although conduction losses associated with additional components increase, switching losses are significantly reduced due to the ZVS operation of main switches. Therefore, total efficiency is improved. Moreover, there is no reverse-recovery problem of the intrinsic body diodes of the switches. To verify the ZVS of the main switches and efficiency improvement of the proposed bidirectional dc-dc converter, theoretical analysis and experimental results from a 200 W prototype are discussed. [ABSTRACT FROM AUTHOR]

This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequency to maximize the converter efficiency. When the parasitic capacitances are low, this solution leads to an identical contribution of the switches and transfer capacitors to the converter output impedance. As the parasitic capacitances increase, the optimum switching frequency decreases. Secondly, optimum capacitor and switch sizes for maximum efficiency are provided. We show that the overdrive voltage strongly impacts the optimum switch width through the modification of their conductance. To support the sizing methodology, a model of the efficiency of switched-capacitor DC/DC converters is developed. It is validated against simulation and measurement results in 65 nm and 0.13 \mu\ m CMOS, respectively. The proposed sizing methodology shows how the converter efficiency can be traded-off for die area reduction and what is the impact of parasitic capacitances on the converter sizing. [ABSTRACT FROM AUTHOR]

Digital control of switching power converters is an area which has seen increased attention in recent years. However, quantization in the feedback loop from the analog-to-digital (A/D) converter and the digital pulse width modulator (DPWM) may cause limit cycle oscillations to manifest, which are generally seen as being undesirable. This paper presents an analysis of the limit cycle behavior found in a multiple-sampled digitally controlled buck converter. The limit cycles which may arise in the system are characterized and conditions to prevent these oscillations from occurring are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a family of integrated multiple output isolated dc–dc converters, in which switches are hybrid utilized. Compared with the conventional separate $N$ -output isolated converter, which employs $2N$ primary switches, only $N$ +1 switches are required in the primary side of proposed converters to independently regulate $N$ secondary output voltages. Therefore, the number of switches is greatly reduced, contributing to lower cost. In this paper, detailed topology derivation is first introduced. A diversity of integrated multiple output topologies is derived with different cell connections and different cell configurations, including the asymmetrical flyback, forward as well as a half-bridge. Their performance characteristics are different and thus they are suitable for different applications. Then, in order to obtain a comprehensive insight of the proposed converters, a simplified dual-output asymmetrical flyback converter with three primary switches is taken as an example to be introduced in detail. Each output voltage in the converter is regulated with individual duty cycle, and zero-voltage-switching operation is achieved for all switches over the whole load range. Finally, experimental results based on a prototype circuit with two 12-V/3-A and 5-V/4.8-A outputs are also provided to validate converter effectiveness. [ABSTRACT FROM PUBLISHER]

Conventionally, inductor current is sensed and quantized before it can be used by digitally controlled DC-DC converters. These are intuitively done by using two separated functional blocks—an analog current sensor and an ADC. A few research works have investigated other ways of obtaining the inductor current information in the digital domain. This paper proposes an on-chip digital inductor current sensor that combines both the inductor current-sensing and quantization into a single functional block. In this way, the redundancies found in the conventional approach can be reduced and optimizations can be made to save chip area and power consumption. An 8-bit digital inductor current sensor has been designed and fabricated with a UMC 0.13~\mum CMOS process. The measurement results show that the digital sensor can provide digital inductor current information with a conversion time of 225 ns. This can be used by a buck converter with a switching frequency up to 4 MHz. The digital sensor has linear and monotonic input-output transfer curve properties with an LSB of 6.79 mA. It consumes current of 700~\muA at 1.2 V supply voltage. [ABSTRACT FROM PUBLISHER]

This paper presents an efficient CMOS dc-dc converter with fast transient recovery. A fast-transient control operating in conjunction with a linearly scaled gate-driving technique is used to concurrently improve the transient response and light-load efficiency of a dc-dc converter. The controller operates under a pulse-width modulation mode during steady state and enables a saturation mode during transient to attain fast transient response. The linearly scaled gate-driving technique optimizes the gate-driving voltage with respect to the changing load leading to lower gate-driving loss and better light-load efficiency. A prototype chip was implemented using a commercial 0.35-μm CMOS process to validate the proposed techniques. The measurement result shows a 5% increase in light-load efficiency and achieves an overall maximum efficiency of 90%. Moreover, the transient recovery time of a 450 mA step load change is less than 9 μs. [ABSTRACT FROM PUBLISHER]

This paper presents a new type of pulse skipping modulation (PSM) in a dc–dc converter, which is controlled by a voltage mode scheme. The duty ratio of the pulses, instead of being constant as in the conventional PSM, is controlled using a voltage mode control scheme along with a feed-forward path of the input voltage and an adjustable voltage. In the conventional PSM, spectral composition varies nonmonotonically which results in problems due to electromagnetic interference (EMI). We show, both analytically and experimentally, that the proposed scheme results in monotonic spectral behavior for a wide range of input voltage and load resistance. Hence one can obtain the small signal model of the system. Because of the synchronism with the external clock, it facilitates the design of an input filter for reduction of EMI. [ABSTRACT FROM PUBLISHER]

A single-inductor two-input two-output power electronic dc-dc converter can be used to regulate two generally nonsymmetric positive and negative outputs by means of a pulsewidth modulation with a double voltage feedback. This paper studies the dynamic behavior of this system. First, the operation modes and the steady-state properties of the converter are addressed, and, then, a stability analysis that includes both the power stage and control parameters is carried out. Different bifurcations are determined from the averaged model and from the discrete-time model. The Routh-Hurwitz criterion is used to obtain the stability regions of the averaged (slow-scale) dynamics in the design parameter space, and a discrete-time approach is used to obtain more accurate results and to detect possible (fast-scale) subharmonic oscillations. Experimental measurements were taken from a system prototype to confirm the analytical results and numerical simulations. Some possible nonsmooth bifurcations due to the change in the switching patterns are also illustrated. [ABSTRACT FROM AUTHOR]

The application of a novel Takagi-Sugeno (TS) fuzzymodel-based approach to prohibit the onset of subharmonic instabilities in dc-dc power electronic converters is presented in this paper. The use of a model-based fuzzy approach derived from an average mathematical model to control the nonlinearities in power electronic converters has been reported in the literature, but this is known to act as a low-pass filter, thus ignoring all nonlinear phenomena occurring at converter clock frequency. This paper shows how converter fast-scale instabilities can be captured by extending the TS fuzzy modeling concept to nonsmooth dynamical systems by combining the TS fuzzy modeling technique with nonsmooth Lyapunov stability theory. The new method is applied to the current- mode-controlled boost converter to demonstrate how the stability analysis can be directly applied by formularizing the stability conditions as a numerical problem using linear matrix inequalities. Based on this methodology, a new type of switching fuzzy controller is proposed. The resulting control scheme is able to maintain the stable period-one behavior of the converter over a wide range of operating conditions while improving the transient response of the circuit. [ABSTRACT FROM AUTHOR]

This paper discusses the general control problems of dc/dc converters connected in series at the input. As the input voltage is shared by a number of dc/dc converters, the resulting converter relieves the voltage stresses of individual devices and hence is suitable for high input-voltage applications. At the output side, parallel connection provides current sharing and is suitable for high output-current applications. Moreover, series connection at the output side is also possible, resulting in output voltage sharing. Theoretically, from a power balance consideration, one can show that fulfillment of input-voltage sharing implies fulfillment of output-current or of output-voltage sharing, and vice versa. However, the presence of right-half-plane poles can cause instability when the sharing is implemented at the output side. As a consequence, control should be directed to input-voltage sharing in order to ensure a stable sharing of the input voltage and of the output current (parallel connection at output) or output voltage (series connection at output). In this paper, general problems in input-series connected converter systems are addressed. Minimal control structures are then derived and some practical design considerations are discussed in detail. Illustrative examples are given for addressing these general control considerations. Finally, experimental prototypes are built to validate these considerations. [ABSTRACT FROM AUTHOR]

This paper investigates the coexisting fast-scale and slow-scale bifurcations in simple dc/dc converters under peak current-mode control operating in continuous conduction mode. Our focus is the boost converter as it is a representative form of dc/dc converter requiring current-mode control. Effects of varying the input voltage and some chosen parameters on the qualitative behavior of the system are studied in detail. Analysis based on a nonlinear simplified discrete-time model, which takes into account the effects of parasitics, is performed to investigate the coexistence of fast-scale and slow-scale bifurcations, and to identify the different types of bifurcation. Boundaries of stable region, slow-scale bifurcation region, fast-scale bifurcation region, coexisting fast and slow-scale bifurcation region are identified. Experimental measurements of the boost converter are provided for verification of the analytical results. [ABSTRACT FROM AUTHOR]

This paper describes a classification of paralleling schemes for dc-dc converters from a circuit theoretic viewpoint. The purpose is to provide a systematic classification of the types of parallel converters that can clearly identify all possible structures and control configurations, allowing simple and direct comparison of the characteristics and limitations of different paralleling schemes. In the proposed classification, converters are modeled as current sources or voltage sources, and their connection possibilities, as constrained by Kirchhoff's laws, are categorized systematically into three basic types. Moreover, control arrangements are classified according to the presence of current sharing and voltage-regulation loops. Computer simulations are presented to illustrate the characteristics of the various paralleling schemes. [ABSTRACT FROM AUTHOR]

Considering a pulsewidth modulated dc/dc converter as an example, this paper describes a border-collision bifurcation that can lead to the appearance of quasi-periodicity in piecewise-smooth dynamical systems. We demonstrate how a two-dimensional torus can arise from a periodic orbit through a bifurcation in which two complex-conjugate Poincaré characteristic multipliers jump abruptly from the inside to the outside of the unit circle. The torus may be ergodic or resonant. However, in both cases the diameter of the torus develops approximately linearly with the distance to the bifurcation point as opposed to the characteristic parabolic form of the well-known Neimark-Sacker bifurcation. The paper also considers the birth of a torus via a subcritical Neimark-Sacker bifurcation in the piecewise-smooth system. Particular emphasis is given to the development of resonance zones via border-collision bifurcations. [ABSTRACT FROM AUTHOR]

This paper presents a simple unified approach to the design of fixed-frequency pulsewidth-modulation-based sliding-mode controllers for dc-dc converters operating in the continuous conduction mode. The design methodology is illustrated on the three primary dc-dc converters: buck, boost, and buck-boost converters. To illustrate the feasibility of the scheme, an experimental prototype of the derived boost controller/converter system is developed. Several tests are performed to validate the functionailties of the system. [ABSTRACT FROM AUTHOR]

In this paper, a phase control scheme for Class-DE-E dc-dc converter is proposed and its performance is clarified. The proposed circuit is composed of phase-controlled Class-DE inverter and Class-E rectifier. The proposed circuit achieves the fixed frequency control without frequency harmonics lower than the switching frequency. Moreover, it is possible to achieve the continuous control in a wide range of the line and load variations. The output voltage decreases in proportion to the increase of the phase shift. The proposed converter keeps the advantages of Class-DE-E dc-dc converter, namely, a high power conversion efficiency under a high-frequency operation and low switch-voltage stress. Especially, high power conversion efficiency can be kept for narrow range control. We present numerical calculations for the design and the numerical analyses to clarify the characteristics of the proposed control. By carrying out circuit experiments, we show a quantitative similarity between the numerical predictions and the experimental results. In our experiments, the measured efficiency is over 84% with 2.5 W output power for 1.0-MHz operating frequency at the nominal operation. Moreover, the output voltage is regulated from 100% to 39%, keeping over 57% power conversion efficiency by using the proposed control scheme. [ABSTRACT FROM AUTHOR]

A new transfer function from control voltage to duty cycle, the closed-current loop, which captures the natural sampling effect is used to design a controller for the voltage-loop of a pulsewidth modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM) with peak current-mode control (PCM). This paper derives the voltage loop gain and the closed-loop transfer function from reference voltage to output voltage. The closed-loop transfer function from the input voltage to the output voltage, or the closed-loop audio-suceptibility is derived. The closed-loop transfer function from output current to output voltage, or the closed loop output impedance is also derived. The derivation is performed using an averaged small-signal model of the example boost converter for CCM. Experimental verification is presented. The theoretical and experimental results were in good agreement, confirming the validity of the transfer functions derived. [ABSTRACT FROM AUTHOR]