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This work proposes a 2-dimensional programable SRAM-based PUF. The selection of challenge groups, orders, and sequence lengths dominates the responses with challenge-response pairs (CRPs) by order of rows $^{\mathrm {(sequence~\textrm {}length- 1)}} \times $ columns $^{\mathrm {(sequence~\textrm {}length - 1)}}$. The PUF bit cell has split word-lines with vertical and horizontal connections, the bit-lines are placed orthogonally to generate one-bit data with four cells, the entropy source is enriched to 24 transistors. The proposed PUF supports multiple data maps from a single chip. A test chip was fabricated in 65 nm CMOS technology. Under 0.8V and 20 °C (nominal point), the bit error rate reaches 3%. In a single chip, the hamming distance achieves 42.49% within the same group and different orders of challenges, and 47.32% within the different groups of challenges (when the sequence length is 5). The measured inter-hamming distance between chips is improved to 49.47%. [ABSTRACT FROM AUTHOR]

A novel 4T2C ternary embedded DRAM (eDRAM) cell is proposed for computing a vector-matrix multiplication in the memory array. The proposed eDRAM-based compute-in-memory (CIM) architecture addresses a well-known Von Neumann bottle-neck in the traditional computer architecture and improves both latency and energy in processing neural networks. The proposed ternary eDRAM cell takes a smaller area than prior SRAM-based bitcells using 6–12 transistors. Nevertheless, the compact eDRAM cell stores a ternary state (−1, 0, or +1), while the SRAM bitcells can only store a binary state. We also present a method to mitigate the compute accuracy degradation issue due to device mismatches and variations. Besides, we extend the eDRAM cell retention time to $200~\mu \text{s}$ by adding a custom metal capacitor at the storage node. With the improved retention time, the overall energy consumption of eDRAM macro, including a regular refresh operation, is lower than most of prior SRAM-based CIM macros. A $128\times 128$ ternary eDRAM macro computes a vector-matrix multiplication between a vector with 64 binary inputs and a matrix with $64\times 128$ ternary weights. Hence, 128 outputs are generated in parallel. Note that both weight and input bit-precisions are programmable for supporting a wide range of edge computing applications with different performance requirements. The bit-precisions are readily tunable by assigning a variable number of eDRAM cells per weight or adding multiple pulses to input. An embedded column ADC based on replica cells sweeps the reference level for $2^{\mathrm {N}}-1$ cycles and converts the analog accumulated bitline voltage to a 1-5bit digital output. A critical bitline accumulate operation is simulated (Monte-Carlo, 3K runs). It shows the standard deviation of 2.84% that could degrade the classification accuracy of the MNIST dataset by 0.6% and the CIFAR-10 dataset by 1.3% versus a baseline with no variation. The simulated energy is 1.81fJ/operation, and the energy efficiency is 552.5-17.8TOPS/W (for 1-5bit ADC) at 200MHz using 65nm technology. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit multi-channel resistor–resistor-string digital-to-analog converter (RRDAC) using a shared R-string scheme for an area efficient display source driver. The proposed scheme relaxes the required equivalent resistance value of R-string of each channel by sharing a channel R-string that is simultaneously connected to the same tap of a global R-string. Thus, the overall DAC size can further be minimized while maintaining the same accuracy. That is, if the proposed scheme is implemented with the same size as the conventional RRDAC, higher accuracy can also be achieved. For the verification of shared resistor string scheme, a 12-bit RRDAC was fabricated using 0.35- $\mu$ m standard CMOS technology. Compared with the conventional RRDAC, the proposed design showed a 15% reduction in size, a DNL of 0.49 LSB and an output voltage deviation of 9. 3mV for eight different chips. Also, the area per channel was 0.0465 mm2. [ABSTRACT FROM AUTHOR]