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This paper describes mounting of standard surface mount component packages on a paper substrate using an industrial solder process with a low-temperature solder. The use of paper as a substrate for printed flexible electronics is becoming more and more widespread as an alternative to the more commonly used plastic substrates, such as polyethylene and polyimide. Paper has the benefits of being environmentally friendly, recyclable, and renewable, as well as inexpensive. It is shown that it is possible to mount standard surface mount device components on paper substrates using low-temperature solder in an industrial soldering process. The contact resistances obtained are mostly low, although the yield of functioning contacts is low. The reason is cracking of the substrate coating layer that goes through the printed silver tracks. It was observed that the cracks appear mostly close to the contact pads, the most likely cause is thermal mismatch between the coating layer and solder and also thermal expansion of the photo paper resin coating. The smallest component package size, 0201, resulted in the highest yield of >80% with decreasing yield for larger package sizes. [ABSTRACT FROM AUTHOR]

The European Union (EU) implemented the waste electrical and electronic equipment (WEEE) and restriction of hazardous substances (RoHS) directives in July 2006. To fulfil the environmental ethos of these EU directives, a printed circuit board (PCB) was developed based on a currently mass-manufactured board, but using a substrate of paper card, with interconnecting tracks added using conductive ink via a printing process. Components were bonded to the tracks using electrically conductive adhesives via an industry-based manufacturing line. During this investigation, paper card substrates of varying surface roughness were examined to establish the effect of substrate surface roughness for printing an interconnecting pattern for single-sided boards. Four degradable card substrate types with surface roughness values varying from 0.25 to 2.66 \mum were trialled. The impact of substrate surface roughness on track resistance was investigated and a correlation between increased substrate roughness and a reduction in track resistance was established, a reduction in track resistance of up to 56% was observed. Flammability analysis of the substrates was performed in accordance with BS61189-2, while mechanical, electrical, and functional tests were undertaken inline with international standards. The developed PCBs were deemed to have met this established criteria, thus opening the possibility of producing a WEEE/RoHS-compliant environment-friendly PCB. [ABSTRACT FROM PUBLISHER]

An introduction is presented in which the editor discusses various papers within the issue on topics including embedded dynamic random access memory, micro-electromechanical systems and circuit fabrication methods for active matrix organic light emitting diodes.

This paper describes a systematic approach to design field-programmable gate array (FPGA) package for high-power applications. As the power consumption is up to multihundred watts, not only the heat dissipation becomes a challenge, but the temperature-induced reliability concerns also mount up in the high current and noise-sensitive packages. Two most profound phenomena are substrate electromigration (EM) and package decoupling capacitor time-dependent dielectric breakdown (TDDB). The impact of EM is on maximum current-carrying capability, and impact of TDDB is on voltage noise suppression capability. However, we find both traditional static way of EM calculation and the legacy design considerations are oversimplified and insufficient for high-power products. In this paper, we report an enhanced methodology to derive substrate EM failure rate from composite current and temperature distributions. Moreover, we incorporate capacitor TDDB into the design flow to optimize capacitor lifetime for effective voltage noise suppression. In the end, we apply the electrical and thermal co-design to a 16-nm, 200-A, high-power FPGA meeting all current and dynamic noise specifications. [ABSTRACT FROM AUTHOR]

In this paper, we apply a level-set (LS) topological optimization (TO) algorithm to the design of multi-material heatsinks suitable for electronics thermal management. This approach is intended to exploit the potential of metal powder additive manufacturing technologies, which enable the fabrication of complex designs. This paper details the state-of-the-art in TO before defining a numerical framework for optimization of two-material and three-material based heatsink designs. The modeling framework is then applied to design a pure copper and a copper–aluminum heatsink for a simplified electronics cooling scenario and the performance of these designs are compared. The benefits and drawbacks of the implemented approach are discussed, along with enhancements that could be integrated within the framework. A benchmarking study is also detailed, which compares the performance of topologically optimized heatsink against a conventional pin-fin heatsink. This is the first time that TO methods have been assessed for multi-material heatsink design where both conduction and convection are included in the analysis. Hence, the reported paper is novel in its application of a state-of-the-art LS topology optimization algorithm to design multi-material structures subject to forced convective cooling. This paper is intended to demonstrate the applicability of TO to the design of multi-material heatsinks fabricated using additive manufacturing processes and succeeds in this objective. This paper also discusses challenges, which need to be addressed in order to progress this modeling as a design approach for practical engineering situations. The presented methodology is able to design thermal management structures from a combination of aluminum and copper that perform similar to pure copper but utilizing less expensive materials, resulting in a cost-benefit for electronics manufacturers. [ABSTRACT FROM AUTHOR]

Traditional semiconductor packaging techniques and materials have been working well for conventional Si devices, which usually operate at temperatures up to 175 °C. As the operating temperature increases, these techniques exhibit failures such as bulk flows, volume shrinkage, brittleness and subsequent cracking, and deterioration of dielectric strength. For the new wide-bandgap power devices, which work at voltages as high as 1200 V and junction temperatures as high as 250 °C, there is currently no known dielectric material to encapsulate and protect the active devices. This paper summarizes novel solutions for high-temperature dielectric materials for encapsulating high-power semiconductor devices without any dielectric breakdown and also without introducing excessive thermal, electrical, and mechanical stresses to the encapsulated devices. Polymer dielectric candidates investigated in this paper include cyanate ester-based resin and silicone-based resin. In addition, conformal coating approaches that include alumina deposited by atomic layer deposition (ALD) technique and tetrahedral amorphous carbon (ta-c) deposited by filtered cathodic vacuum arc technique were evaluated in this paper. Dielectric strength performance of the material combinations with respect to temperatures was evaluated. Among the polymer encapsulants, a silicone resin with silica fillers was determined to be the prospective candidate. Breakdown voltage and leakage current of the silicone-based encapsulant with and without the conformal coating was measured by breakdown tests. It was determined that the ta-c conformal coating deteriorates the dielectric performance of the encapsulant, while the alumina thin film deposited by ALD approach reduces the leakage current of the encapsulation material and also increases the breakdown voltage of the silicone encapsulant. Thus, the combination of alumina thin film deposited by ALD approach along with the silicone encapsulant is recommended for this application, involving high temperature and high voltage. [ABSTRACT FROM AUTHOR]

In this paper, the transient experimental validation of the convolution-based fast thermal model (FTM) for 3-D integrated circuits is presented. The methodology is proven to be applicable to analyze the temperature evolution of real devices. A low-power package configuration with two different power dissipation scenarios, hotspot (HS) in the corner and HS in the center of the active region, has been considered for the validation. In this way, the importance of the package thermal impact on the definition of the final temperature profiles is highlighted. The error between the measurement and the FTM results remains always below 2.3 °C/W. Moreover, the model has been validated with respect to case studies concerning duty cycles of different durations. This proves the applicability of the model in defining the allowed duration of the chip activity before a maximum threshold temperature is reached. Finally, in this paper, the possibility to use a variable time-step approach in the transient FTM is presented together with the option of computing the temperature in individual points only. This is possible maintaining the same accuracy as if the fully resolved temperature maps would be calculated. [ABSTRACT FROM AUTHOR]

The conventional design of notebook PCs configured with an optical disk drive suffers from structural durability problems that are indicative of potentially high defect rates. Companies have been attempting to reduce the size of assembly parts to pursue compactness, but the elimination of these materials might negatively affect structural stability, which is fundamentally important to all high-technology products. The Six Sigma methodology applied in this paper aims to improve quality performance and eliminate redesign waste and unnecessary handoffs according to customer requirements. This paper presents a case study using the define, measure, analyze, improve, and control (DMAIC) procedure. Several optimization techniques, such as response surface method (RSM) and computational intelligence, are adopted to optimize the significant factors that affect the module design and structural strength index during compression. Implementation results demonstrate that computational intelligence outperforms RSM. It shows computational intelligence reveals a good ability to solve the parameter optimization problems. [ABSTRACT FROM AUTHOR]

In this paper, a novel mymargin soldering technique that improves the fabrication process of empty substrate integrated waveguide (ESIW) devices is presented. Up until now, in order to fabricate an ESIW device, the tin solder paste was distributed, before assembling, on the contact surface between layers, in order to ensure a good electrical contact. This process has a low degree of repeatability (random soldering thickness and distribution of tin) and reliability (a significant number of nonworking prototypes due to tin overflow). In this paper, we propose the mechanization of a set of plated vias just next to the metalized walls of the ESIW in the central layer. Next, in the top and bottom covers that close this ESIW, additional plated vias are drilled in the same position so that, when the device is assembled (using screws or rivets), metalized holes can be seen passing through the whole structure from top to bottom. These holes are then used as soldering vias that can guide the tin paste straight to the point where it is needed. When the paste is dried, soldered vias ensure a very good electrical contact between layers. In addition, the fluid tin fills any small gap that appears between layers, thus providing a very good electrical contact and mechanical union. This novel soldering technique has been validated with experimental results. Several prototypes of filters centered at 13 and 35 GHz have been fabricated, proving the repeatability and reliability of the proposed soldering technique. [ABSTRACT FROM AUTHOR]

This paper studies signal integrity problems caused by parasitic parameters and skin effect of bond wire. Based on the low-pass filter theory, this paper proposes a new design of bond-wire interconnection circuit in microwave multichip modules. The transmission characteristics of bond-wire interconnection circuit can be significantly improved when the length of bond wire is fixed. A compensation structure based on the third-order Butterworth low-pass filter is presented. In comparison with the uncompensated structure, the bandwidth of the bond wire is increased by 25.1 GHz with the proposed design. Moreover, a compensation structure based on the fifth-order Chebyshev low-pass filter is presented, too. In comparison with the uncompensated structure, the parasitic effects of the bond wire are minimized, and the bandwidth is increased by 56.8 GHz with the proposed design. The microwave circuit design software and electromagnetic field software were used to model and analyze the microwave characteristics of this circuit. The circuit was verified by the results of the simulation. [ABSTRACT FROM AUTHOR]

The fast development of flip-chip (FC) devices has helped to keep ICs on pace for Moore’s law. FC devices have many buried interfaces, the structures of which all need to be investigated in order to optimize them. It is extremely difficult to examine molecular structures of buried interfaces in samples with multiple layers due to the lack of appropriate analytical tools. In this paper, real FC-on-leadframe devices, manufactured by Texas Instruments Incorporated, were investigated using the intrinsically interface-sensitive technique and sum-frequency generation (SFG) vibrational spectroscopy. By milling down the Si wafer, we can probe the polyimide (PI)/mold compound (MC) interface. By milling down further, we can examine the air/MC and the MC/leadframe (LF) interfaces. Methylene and methyl groups were detected from each of the three interfaces, and the orientation of methyl groups was determined at each interface. It was calculated that at the PI/MC interface, the methyl group tilt angle was 20° (from the surface normal). For the air/MC interface, the tilt angle was 43.5°, and for the LF/MC interface, the tilt angle was measured to be 45°. The deduced different methyl orientations at the two buried solid/solid interfaces can be interpreted by the interfacial interactions. The PI surface is more hydrophobic than the LF surface; therefore, it has more favorable interactions with the hydrophobic methyl groups, leading to a more “standing up” (smaller tilt angle) position for the methyl groups at the PI/MC interface. In this paper, SFG was successfully applied to study the buried interfaces in real devices. The SFG method used in this paper is general and can be applied to other real-world, complicated thick systems. [ABSTRACT FROM AUTHOR]

This paper discusses the design, fabrication, and characterization of packaged planar inductors with magnetic material [nickel zinc (NiZn) ferrite]. Inductors are designed specifically for Internet of Things (IoT) applications based on power loss in an IoT architecture. Different spiral inductor geometries are demonstrated on a printed wiring board with varying thicknesses using a stencil printing process. The magnetic material can be applied to one or both sides of the inductor and, therefore, provides size reduction. This paper examines the role of varying dimensions on inductor performance along with model-to-hardware correlation. The fabrication process demonstrates inductance increase through a very simple procedure for applying a magnetic material on both sides of the inductor, while having flexibility to customize the geometry for minimal power loss in an IoT architecture. With NiZn ferrite material added to both sides of the inductor, the inductance increases between approximately 60% and 80% for the two substrate thicknesses studied, as compared to air-core inductors. [ABSTRACT FROM AUTHOR]

This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- \mu \textm line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 20~\mu \text{m} or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs. [ABSTRACT FROM PUBLISHER]

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips. [ABSTRACT FROM PUBLISHER]

In this paper, wafer-level AuSn/Pt solid–liquid interdiffusion bonding for hermetic encapsulation of microelectromechanical systems (MEMS) is evaluated. Although AuSn is used for bonding of ICs, the implementation of AuSn diffusion bonding in MEMS applications requires thorough understanding of its compatibility with the complete layer stack including adhesion, buffer, and metallization layers. Partitioning of the layer stacks is possible in MEMS devices consisting of several silicon wafers since the device wafer carrying functional structures and the encapsulation wafer have different restrictions on process integration and applicable metal deposition techniques. In this paper, CMOS/MEMS compatible sputtered platinum is utilized on the device wafer as a contact metallization for Au–Sn metallized cap wafer. The role of the platinum layer thickness as well as the nickel and molybdenum buffer layers on mechanical reliability were tested. The mechanical shear and tensile tests were performed for samples after bonding as well as after high-temperature storage and thermal shock tests. The results were rationalized based on the combined microstructural, thermodynamic, and fracture surface analyses. High-strength and thermodynamically stable bonds were achieved, exhibiting shear strength up to ~180 MPa and tensile strength up to ~80 MPa. Platinum was consumed completely during bonding and was observed to dissolve mainly into the (Au,Pt)Sn phase. Thicker platinum layer (200 versus 100 nm) increased the (Au,Pt)Sn phase thickness and resulted in higher strength. The molybdenum buffer layer under the platinum metallization increased the tensile strength significantly. [ABSTRACT FROM AUTHOR]

Magnetodielectric (MD) materials find application in many areas of microwave engineering, and therefore, measurement of their dielectric and magnetic properties is very important. This paper presents a novel MD material characterization method using the cavity perturbation technique (CPT) with substrate-integrated waveguide (SIW) cavity resonators. Frequency dependent complex permittivity and permeability of MD material can be extracted with a single SIW cavity structure by inserting the sample material into different locations. The fundamental theory of CPT is explained and its analysis for SIW cavity is discussed. Cobalt nanoparticles are synthesized with a fluoropolymer matrix to realize the MD materials and their properties are measured in the frequency range 1–4 GHz. The effect of volume fraction and density of the synthesized MD materials on the dielectric and magnetic properties has been studied. [ABSTRACT FROM AUTHOR]

Welcome to the Special Topics Section dedicated to the 2016 Holm Conference on Electrical Contacts. This special section contains eight high-quality papers that comprehensively describe the state of the art and potential future directions for topics of great interest to our readers. The Editor-in-Chief (EIC), in consultation with the other EICs, Associate Editors (AEs), and domain experts, selects the topics for the special sections, and a Guest Editor or AE (GE/AE), who is a leading expert in the technical area, then directs the solicitation and peer review of the papers. In cases where the GE/AE is also an author, the EIC is responsible for the peer review to avoid any real or perceived conflicts of interest. [ABSTRACT FROM AUTHOR]

Ball grid array (BGA) package components are widely used in various electronic products, as they shorten the conductive path and greatly reduce the interference during current transmission. The BGA component solder ball has little flexibility for distortion, which may cause stress concentration and solder joint cracking. Red ink dye stain analysis testing can visually analyze the cracking area and the interface of the solder joint. At present, most companies use failure analysis (FA) specialists to observe the components and circuit board end images with a microscope. As component packaging technology becomes more complex and the number of input–output (I/O) signals of the chip increases sharply, FA operations require a long time and may be misjudged due to personnel fatigue and subjective determination. This paper aims to develop a machine vision image recognition system for intelligent decision analysis to judge the severity of solder ball cracking and the cracking interface type. This system uses charge-coupled devices (CCDs) to obtain the image. First, this paper uses affine transformation compensation to perform horizontal correction, which recognizes the actual position coordinates of each solder joint, estimates the solder ball according to the Hough Circle to obtain the center and the radius of the solder ball, and then a 2-D vector map (Gerber) file is used to establish the mask, and the region of interest (ROI) in the image feature is obtained through the iterator of the pixel access program. Second, the color space is converted from red, green, and blue (RGB) to hue, saturation, and value (HSV) to reduce the effects of light variations during image capture. This paper develops the range analysis model (uses the multiple-threshold method to judge whether a particular pixel in an image has the cracking (color) feature, as well as its cracking interface), and uses a morphology filter to filter image noise (filter pixels of overlapping features). The verification results show that the system developed in this paper and FA specialists have a consistency of more than 85% in the judgment of the severity of the cracking, and the false alarm ratio and the escape ratio of the system are about 9% and 16%, respectively. Regarding the judgment result of the solder ball cracking interface type, the consistency reaches 98%, which shows that the automatic failure identification system for solder joints, as developed in this paper, can effectively assist red ink solder joint FA. [ABSTRACT FROM AUTHOR]

This paper introduces a fully automated greedy algorithm for the construction of parameterized behavioral models of electromagnetic structures, targeting at the same time uniform model stability and passivity. The proposed algorithm is able to determine a small set of parameter configurations for which an external solver provides on-the-fly the sampled scattering parameters of the structure over a predetermined frequency band. These samples are subjected to a multivariate rational/polynomial fitting process, which iteratively leads to a parameterized descriptor realization of the model. The main novel contribution in this paper is the adoption of a model-based approach for the adaptive augmentation of an initially small set of frequency responses, each corresponding to a randomly selected parameter configuration. In particular, the locations of the in-band passivity violations of intermediate macromodels constructed at each iteration are used as a proxy for the model-data error in those regions where input data are not available. This physics-based consistency check, which is enabled by recent developments in multivariate passivity characterization based on Skew-Hamiltonian–Hamiltonian (SHH) spectra, is combined with standard space exploration metrics to obtain a small-size and automatically determined distribution of points in the parameter space, leading to the construction of an accurate macromodel with a very limited number of external field solver runs. The embedded passivity check and enforcement process guarantees that either the final model is passive throughout the parameter space or the residual violations, if present, are negligible for practical purposes. Several examples validate the proposed approach for up to three concurrent parameters. [ABSTRACT FROM AUTHOR]

The definition of ingress protection (IP) rating is a classification that must be declared by the manufacturer for both the LED drivers and all other electronic devices. This definition indicates how the electronic circuits have protection against water, dust, and other solid objects. Therefore, the requirements of this declared definition must be met. In this paper, this class definition for the LED driver circuits used in street lighting is declared as IP66. In order to ensure IP66 class protection requirements, the LED driver circuit is placed in a closed box. However, since the box is completely closed, the heat cannot be transferred sufficiently to the outside, even if the box is made of thermally conductive aluminum material. This may cause the LED driver circuit to malfunction. Therefore, in order to fulfill the IP class requirement and to contribute to the solution of the temperature problem, the box of the driver card is filled with a thermal-conductive potting material. However, this filling material can contribute to the solution of thermal problems, but also has a number of drawbacks. In this paper, the effect of the potting material on LED driver circuits to reliability and electromagnetic compatibility performance is investigated experimentally and comparatively. [ABSTRACT FROM AUTHOR]

Accurate peeling off and transferring of microchips play a critical role in LED die sorting technology. Generally, sorting efficiency of more than 36 KUPH, and an alignment deviation less than 1 mil ($25.4~\mu \text{m}$) is required. High precision position control and cooperation of multifactors should be implemented precisely. Among all the factors, the film deformation is an important one. As the sorting proceeds, dies are peeled off from substrates one by one, and the adhesive substrate is penetrated through a hole each time. As the number of stripped chips increases, viscoelastic deformation of tape surface takes place and tiny position shift of die adhered on tape arises. This shift may cause a negative impact on the peeling process. In this paper, linear viscoelastic deformation impact is tested with well-designed experiments. To evaluate the effect of tape deformation accurately for sorting the performance, stochastic Petri net model of the transferring system with dual-independent arms is formulated to analyze the influence of factors. On this basis, strategy on coordinating motion control and scheduling is proposed, rational velocity section is planned, and the active position compensation of supply platform is set, so that the die can be peeled off correctly and efficiently. Finally, to improve sorting performance, methods on active compensation of aligning platform are proposed and proven effective by an experimental validation. [ABSTRACT FROM AUTHOR]

In this paper, a closed-form mathematic equation that governs gas ingression of hermetic packages is derived from first principles and applied to moist air and water vapor ingression conditions. The equation models internal gas partial pressure change as a function of time, external conditions, and package characteristics. The equation provides the theoretical basis for direct comparisons of ingression behaviors of different gases into hermetic packages. Comparing the rates of internal air pressure increase due to air ingression and water vapor partial pressure buildup due to water vapor ingression, the authors theorize that vacuum decay may present a greater challenge to the performance of microelectromechanical systems (MEMS) devices within hermetic packages than that of water vapor content induced corrosion failures. This paper also examines gas ingression of hermetic enclosures with multiple layers of seals. [ABSTRACT FROM AUTHOR]

Closed-form design equations and exact numerical examples are presented for the proposed multifunctional rat-race couplers in the mentioned paper (IEEE Trans. Compon., Packag., Manuf. Technol., vol. 7, no. 6, pp. 944–955, Jun. 2017). Correct design parameters and frequency responses are provided for the readers. It is obvious that the four arbitrary terminated impedances of rat-race couplers are completely correct, despite whether short (long) electrical lengths are 90° (270°) or not. Finally, some small corrections and modifications are given. The provided examples clearly verify that our proposed design method is accurate, general, and rigorously correct. [ABSTRACT FROM AUTHOR]

In this paper, a completely automated computer-aided design (CAD)-to-print process flow for hybrid direct-write 3-D printing (3DP) was produced. We adapted this capability to manufacture a meandering conductive trace formed into a meandering arbitrary interconnect in the shape of a 3-D pretzel that is completely embedded in dielectric. The conversion between g-code and pgm-code was demonstrated for hybrid 3DP between metal and dielectric materials. This paper produced a reliable automated process that can potentially be used to manufacture arbitrary 3-D circuits. This paper also identified the need for better slicing techniques for hybrid manufacturing of interconnects. [ABSTRACT FROM AUTHOR]

Wireless power transfer (WPT) is an ideal power delivery solution for many light-load applications, such as for the Internet of Things. A regulated solution for WPT may utilize a power distribution unit (PDU). Previous works have designed planar inductors for integration with switched-inductor buck regulators, but these inductors will not be as efficient for light-load applications. This paper reevaluates the inductor loss for light-load applications by taking into account the frequency spectrum of the inductor current. Using this revised analysis, a planar inductor with screen printed NiZn ferrite epoxy composite magnetic core is designed for an RF near-field coupling system with 1–10-mW load power. In measurement with a 6-MHz buck converter, the PDU with designed inductor demonstrated up to 3% improved efficiency compared to surface-mount technology inductor in the pulse-frequency modulation mode and pulsewidth modulation mode. The designed embedded inductor was subsequently demonstrated in an integrated, compact RF near-field coupling system with peak 43% system efficiency. [ABSTRACT FROM AUTHOR]

A single-phase high power electronics package is designed and developed in this paper. The developed power package achieves a significant thermal performance improvement compared with the conventional wire-bonded power package. The improvement is attributed to two features of the package design. First, the SiC chips are embedded into the active metal brazed (AMB) substrates with specially designed cavities, as such the heat transfer path from the embedded SiC chips to the liquid-cooled heat sink attached to the bottom side of the AMB substrate is shortened. Hence, the thermal performance of the package is improved. Moreover, customized copper clips are introduced as the electrical interconnections between the SiC chips and the top metal layer of the substrate at the same level, and the top surface of the power package remain flat. As such another heat sink can be added to the top side of the package to further improve the thermal performance of the power package through the double-side cooling (DSC) scheme. The simulation results show that the junction-to-case thermal resistance (Theta JC) of the optimized power package is about 50% less than the Theta JC of the conventional wire-bonded power package with the same package size and the same power rate. Further applying the DSC scheme to the proposed power package, which is not suitable to the conventional wire-bonded power package, the Theta JC of the proposed power package reduces another 20%. In addition, the effects of the core layer (i.e., material and thickness) and the metal layer (i.e., materials and thicknesses) of the AMB substrate, as well as the die attach (i.e., material and thickness) on the Theta JC of the proposed power package are investigated systematically. As such the thermal performance of the power inverter package is further elaborated. Finally, the thermally enhanced power package is fabricated and assembled. Thermal characterization has been conducted, and the thermal performance of the developed power package has been evaluated. The simulation results and characterization results match well with each other. [ABSTRACT FROM AUTHOR]

This paper reports on design of novel balanced bandpass filters (BPFs) using quarter-wavelength stub resonators. For the design purposes, differential-mode (DM) and common-mode (CM) half-equivalent circuits are established and analyzed carefully. In this paper, CM noise is introduced into the filter and dissipated on the resistors on periodic bands. First, a balanced BPF topology based on conventional quarter-wavelength stub filter is presented. By symmetrically introducing series matching resistors to the ground at the center of the stub, CM noise can be rejected either reflectively or reflectionlessly without affecting DM performance. The harmonic property of stubs provides periodic CM suppressing response as long as the resistor has no serious parasitic reactance. By doing so, CM noise can be suppressed under a certain level at all frequencies. However, the harmonic property also leads to some spurious passbands. This defect can be avoided by an improved filter topology with two additional capacitors. To reserve the CM feature, the corresponding DM and CM half equivalent circuits are developed as well. The proposed layouts are fabricated on a two-layer printed circuit board. The resulting experimental circuits exhibit the expected electrical performance, forming balanced BPFs with CM noise suppression level over 12 dB at all frequencies, and show an agreement with the simulated results. [ABSTRACT FROM AUTHOR]

This paper investigates polymer/metal hybrid bonding structure using conventional polyimide and modified polyimide-like material. Adhesion properties between bonding material and passivation layer were evaluated by four-point bending method, atomic force microscopy, water contact angle measurement, and X-ray photoelectron spectroscopy. Various annealing temperatures were applied to verify the reliability under thermal stress. The results show that the modified polyimide-like material with the curing temperature below 250 °C has better adhesion than the conventional polyimide. This modified polyimide material can be used in low-temperature hybrid bonding technology for advanced integration. [ABSTRACT FROM AUTHOR]

Three-dimensional large scale integration (3D-LSI) packaging is crucial toward obtaining increased circuit density within a small footprint. In a 3D-LSI package, chip-to-chip interconnection is typically obtained using through-silicon vias and microbumps. In particular, microbumps realized by nanoparticle deposition (NPD) are promising to obtain high-density interconnections. However, the effect of temperature on the mechanical properties (i.e., hardness) of NPD bumps is little understood. This paper seeks to investigate the influence of temperature on the hardness of NPD bumps, with reference to NPD films. The results obtained suggest a significant reduction in the NPD bump hardness from room temperature to 200 °C. In particular, the hardness was observed to be mainly dependent on temperature rather than grain size, as the grain microstructures obtained at room temperature and 200 °C are similar. Overall, these results suggest a simple approach to control the NPD bump compression during flip-chip bonding, where the hardness-temperature data for the NPD bumps suffices to estimate for the bump compression during flip-chip bonding. [ABSTRACT FROM AUTHOR]

The abnormal rise in contact temperature in switchgear may lead to overheating or even explosion. It is necessary to monitor the rise in real contact temperature to ensure the safety and stability of switchgear. The accurate measurement of real contact temperature is still a problem, and the continuous state of switchgear cannot be assessed accurately by the temperature monitor. In this paper, a particular installation scheme of temperature sensor is put forward and a calculation algorithm for temperature rise of tulip contacts by the measured temperature of bus bar in real time based on artificial neural network (ANN) is established. An electromagnetic-thermal-fluid coupled simulation model for 10-kV/4000-A switchgears was built, and the thermal characteristic was studied taking the influential factors such as load current, ambient temperature, and contact resistance into consideration. The effectiveness of simulation model is discussed by the comparison to temperature rise experiment. Then, an ANN with three layers of structure is established to calculate the temperature of tulip contacts. The sensitivity and accuracy of network are calculated and verified. The results of this paper may provide a novel method for the monitor of switchgear temperature and assess continuous condition of high-current switchgear. [ABSTRACT FROM AUTHOR]

Fine-pitch interconnection technology in electronic packaging has become very important because of electrical interconnection issues such as high contact resistance and open-/short-circuit failure. Nanofiber anisotropic conductive films (ACFs) and nanofiber sheet ACFs (NS ACFs) have been developed and reported by our research group to address the challenges for fine-pitch interconnection problems. However, they require complicated fabrication processes such as electrospinning, thermal compression, and plasma etching. In this paper, anchoring polymer layer (APL) ACFs and their fabrication process are introduced. The goal in employing the APL ACFs was to simplify the complex fabrication steps of nanofibers and NS ACFs by coating methods without compromising electrical performance. With the APL coating method, the electrospinning, thermal compression, and plasma etching steps can be reduced to a single process. Nonetheless, APL ACFs exhibit excellent electrical conduction at 20- $\mu \text{m}$ fine-pitch interconnections by successfully suppressing the movement of conductive particles in the ACF. The capture rate of the APL ACFs was 78%, which was comparable to the value 81% of NS ACFs. APL ACFs open the possibility of cost-effective production of ACFs interconnection materials for fine-pitch applications. Therefore, we use the word “anchoring” to suppress the movement of conductive particles during resin flow. In this paper, we discuss the fabrication process of APL structure and electrical properties of APL ACFs. [ABSTRACT FROM AUTHOR]

In power electronic applications, due to switching components, the inverter dc-bus generates current pulses at low frequencies and high frequencies (HFs). Usually, a dc-bus capacitor is sized to absorb the current peaks at the switching frequency and to stabilize the dc voltage. For decoupling the HF harmonics, an additional capacitor is required. This decoupling capacitor needs to have a low impedance over a wide range of frequencies. However, their performances for the HF range are highly limited by their stray inductance. In order to minimize the need for an additional decoupling capacitor at HFs, this paper proposes to improve the connections of the dc bus capacitor. Busbar configuration and printed circuit board allow reducing parasitics of the cabling. Several types of interconnections are proposed and characterized in this paper. Both two-terminal and four-terminal capacitors are evaluated and compared regarding operating frequency ranges. The measurement and modeling results show a significant improvement for HF decoupling by using quadrupole coaxial connections. [ABSTRACT FROM AUTHOR]

To investigate and quantify the radiation emission of an electronic package model, the partial element equivalent circuit method combined with the field equivalence principle is developed in this paper and used for the near-field radiation prediction. Furthermore, this paper presents a novel electromagnetic bandgap (EBG) design to suppress the electromagnetic radiation. The simulation results obtained by the proposed method have been validated against the measurement; moreover, the simulation and measurement results demonstrate the noise suppression ability of the new designed EBG structure, which can be used to reduce the electromagnetic radiation of the package. [ABSTRACT FROM AUTHOR]

The dependence of self-inductance and mutual inductance on bonding wire (BW) geometric profile has been studied in several papers. This paper will present a method using a BW-geometric-profile-dependent term to include this dependence in a simple model of BWs. The model element values will be calculated only from geometric dimensions. An experimental structure of two BWs in parallel planes has been fabricated based upon glass substrate technique for verification. A good agreement was obtained up to 8 GHz in comparison to electromagnetic simulation and measurement. [ABSTRACT FROM AUTHOR]

The data center industry focuses on initiatives to reduce its enormous energy consumption and to minimize its adverse environmental impact. Modular data centers provide considerable operational flexibility in that they are mobile and are manufactured using standard containers. This paper develops steady-state energy and exergy destruction models for modular data centers with the open-source EnergyPlus software package. Three different cooling approaches are examined: direct expansion (DX) cooling, evaporative cooling (direct evaporative cooling, DEC, in this study), and free air cooling (air-side economization in this study). This paper shows that for hot and arid climates like those in the southwestern U.S., augmenting DX cooling with evaporative and free air cooling can result in energy savings of up to 38% and 36%, respectively. This paper also applies exergy analysis to suggest that the Energy Reuse Effectiveness of the data center increases with decreasing ambient (outdoor) temperature and increasing server inlet–outlet temperature difference. Furthermore, simulations indicate that the use of passive cooling techniques (e.g., DEC and free air cooling) decrease data center heating, ventilation, and air-conditioning energy consumption, except in extremely hot and humid climates. [ABSTRACT FROM PUBLISHER]

Reliable and long-lifetime electrical contact is a very important issue in the field of radio frequency microelectromechanical systems (MEMS) and in energy transmission applications. In this paper, the initial unstable electrical contact phenomena under the conditions of micro-newton-scale contact force and nanometer-scale contact gap have been experimentally observed. The repetitive contact bounces at nanoscale are confirmed by the measured instantaneous waveforms of contact force and contact voltage. Moreover, the corresponding physical model for describing the competition between the electrostatic force and the restoring force of the mobile contact is present. Then, the dynamic process of contact closure is explicitly calculated with the numerical method. Finally, the effects of spring rigidness and open voltage on the unstable electrical contact behaviors are investigated experimentally and theoretically. This paper highlights that in MEMS systems switch, minimal actuation velocity is required to prevent mechanical bounce and excessive wear. [ABSTRACT FROM AUTHOR]

In this paper, 2.5-D integrated circuits (ICs) using bridge-chip technology are thermally evaluated to investigate thermal challenges and opportunities for such multi-die packages. To this end, the objectives of this paper are twofold. First, thermal benchmarking of a number of 2.5-D integration approaches is performed and compared to 3-D ICs for completeness. Thermal modeling shows that the evaluated 2.5-D integration approaches exhibit similar thermal characteristics, but show significant improvements compared to 3-D IC solutions with the same power consumption. Second, this paper explores bridge-chip-based 2.5-D integrated systems as a function of bridge-chip thickness, thermal interface material properties, microbump properties, die thickness, die thickness mismatch, and die-to-die spacing along with transient analysis to investigate time-domain thermal coupling. Results suggest that a die thickness mismatch of 100 \mu \textm can increase the maximum temperature by 25.8% Therefore, the die thickness mismatch should be kept as small as possible, and the hottest die should be the thickest. Moreover, reducing die-to-die space from 1 to 0 mm increases thermal coupling, and the low-power dice, such as DRAM, can have a temperature increase of 6.1%. [ABSTRACT FROM PUBLISHER]

In this paper, we present a new frequency-tunable filtering power divider structure and its design method. For achieving the frequency filtering characteristic, the power divider uses a single resonator or multiple resonators. One of the unique features of the presented structure is that the last resonator is coupled to the two outputs, and this allows for minimizing the number of the resonators used in the power divider design. For verifying the presented structure and design method, we have designed filtering power dividers using frequency-tunable substrate-integrated resonators. It is shown that the operating frequency of the divider can be adjusted maintaining excellent impedance matching performance. [ABSTRACT FROM PUBLISHER]

This paper presents two microstrip multiband multiplexers using distributed coupling technique. The proposed multiband multiplexers consist of a distributed coupling feeding line, asymmetric stepped-impedance resonators, and output feeding lines. Each pair of resonators controls a respective bandpass channel for good design freedom. By using distributed coupling technique, there is no extra matching network required in the multiplexers. In order to obtain a wide stopband, asymmetric stepped-impedance resonators and asymmetric feeding lines are employed. The operation frequencies of the first multiband multiplexer are at 1, 1.3, 1.6, 1.9, 2.2, and 2.5 GHz, and the second one operates at 1, 1.3, 1.6, 1.9, 2.2, 2.5, 2.8, and 3.1 GHz. The stopband rejection level is better than 20 dB up to 4.6 times the lowest operation frequency. The proposed design concept is validated with the two fabricated multiband multiplexers. The measurements show good agreement with simulations. [ABSTRACT FROM PUBLISHER]

Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF. [ABSTRACT FROM AUTHOR]

3-D integration typically involves multiple chips stacking with large numbers of interconnections within each chip. There are several fundamental technology challenges that need to be addressed in order to realize 3-D integration, such as Cu through-silicon via (TSV) expansion, transistor degradation or open failures on Cu contamination, microbump stress, and so on. The reliability issues on TSV and microbumps are very critical not only for a stacked chip package, but also during wafer-level processes. In this paper, the authors successfully stacked six chips with a thickness of 50 \mu \textm and assessed their reliability. Each chip consists of 122054 bumps with a bump diameter of 10~\mu \textm and a pitch of 20 \mu \textm . These bumps were built directly on TSVs, which have a diameter of 5~\mu \textm . Measured electrical resistance is well matched with calculated electrical resistance. Finally, this paper presents the reliability results of the 3-D IC packages that are embedded in molding compound. [ABSTRACT FROM AUTHOR]

The demand for flexible and wearable wireless systems is increasing exponentially in today’s information-oriented society. These systems are extremely beneficial and applied in a wide spectrum of fields, such as personal communication, medicine, military, firefighting, entertainment, aeronautics, and radio frequency identification. In this paper, the design constraints, fabrication process, flexibility tests, and measurement of flexible and wearable antennas are discussed in detail. Furthermore, the design, fabrication, and testing of a compact flexible ultrawideband antenna are presented. The proposed design has the merits of light weight, ultralow profile (50.8 \(\mu \) m), widebandwidth, mechanical robustness, compactness, and high efficiency. The antenna is also tested against bending effects to characterize its performance in a realistic setup since it is expected to be conformed on curved surfaces and/or flexed during operation. [ABSTRACT FROM AUTHOR]

In this paper, we have shown an analytical technique to scale the power delivery solutions for a given integrated circuit (IC) chip that can draw currents to cause enough inductive noise for the IC to fail. This scaling method will also provide the optimum package solutions to minimize the cost of IC products. This method can be very useful to determine the package and die design methodology at the initial phase of the design cycle of the chip. [ABSTRACT FROM AUTHOR]

Through-silicon-via (TSV) technology permits devices to be placed in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to its many advantages. However, there are some challenges for TSV wafer processes. One of the challenges is TSV wafer thinning process (WTP). In this paper, a dynamic finite element modeling methodology was established and used to study the TSV WTP-induced wafer stress. It was found that wafer surface roughness, TSV wafer thickness, bonding/debonding material, and TSV feature size have impact on TSV wafer stress under the TSV WTP. The impact of wafer thinning-induced stress on mobility change was also discussed in this paper. [ABSTRACT FROM AUTHOR]

During the wafer fabrication process, wafers warp into different kinds of shapes, such as spherical, cylindrical, or saddles. These wafers may exhibit a bistable state, that is, if we apply a certain amount of pressure, they snap into another state. Though these shapes are commonly observed in the real world, we have found that it is extremely difficult to obtain these shapes in finite-element tools, such as ANSYS, because some of these states are not numerically preferred solutions. In this paper, we discuss various methodologies we have used to obtain these shapes in ANSYS. The experiments have been carried out in our fabrication lab to measure the wafer warpage at various stages of wafer fabrication. We have found that when the simulated shape matches the experiment, the warpage or maximum out of plane displacement of the wafer obtained from our simulation matches with 1% with the experimental results as well. Furthermore, ANSYS simulations show that backgrinding increases the warpage by the same amount as observed in the experiments. This paper also discusses the limitations of Stoney's formula. The final goal of this paper is to predict how warpage is going to affect the stresses in the silicon (Si) trenches in a device and if any particular trench design is going to lower the amount of wafer warpage, hence the stresses in Si trenches. refid="sec4"Section IV shows the simulation results of stresses in the Si trenches. Since it would be computationally infeasible to model a full wafer having all the details of the trench structures, a submodeling technique has been adopted to calculate the stresses in the Si trench wall of a warped wafer. These simulation results are compared with micro-Raman spectroscopy measurements of a warped wafer. [ABSTRACT FROM AUTHOR]

The 3-D integrated circuits (3-D ICs) are emerging as a viable solution to enhance the performance of many-core platforms. These architectures generate a high and rapidly changing thermal flux that makes conventional air-cooled devices more susceptible to overheating. Liquid cooling is an alternative that can improve dissipation and reduce thermal issues. Fast and accurate thermal models are needed to appropriately dimension the cooling system at design time. Several models have been proposed to study different designs, but generally with low simulation performance. In this paper, we present an efficient model of the transient thermal behavior of liquid-cooled 3-D ICs. This paper presents an approach with extremely low memory usage and advanced numerical methods to efficiently compute the transient temperature of 3-D ICs. Our experiments show the $100\times $ speedup versus the state-of-the-art models, while maintaining the same level of accuracy, and demonstrate the efficiency of liquid cooling to remove the heat from 3-D many-core platforms. [ABSTRACT FROM PUBLISHER]

This paper presents an on-chip digitally programmable thermal coupling emulation framework, referred to as the field-programmable thermal emulator (FPTE), for online characterization of power pattern, time-varying thermal field, and associated changes in the electrical characteristics of the transistors. A test chip was designed in 130-nm CMOS to validate the test structure. The measurement results demonstrated the ability of FPTE to emulate various power patterns and capture the effects on temperature and circuit performance. The test chip is used to explore and identify thermal coupling. The potential application of FPTE moves beyond thermal package tests and is capable of being used as chip-level thermal condition prediction and management infrastructure. [ABSTRACT FROM PUBLISHER]

This paper deals with the safety devices incorporated in the most commercial 18650 lithium-ion (Li-ion) cells. The systems have been effective at cell level, but with the development of Li-ion cells in module or battery pack configurations, safety device breakdown occurs during battery operation. The 18650 cells include a current interrupt device (CID), which manages cell overcharge by opening the circuitry when an overpressure event occurs. But CID opening under high voltage can undergo electric arcs and it can lead to a thermal runaway in the most extreme cases. First, in this paper, the general risks that exist in batteries and the related protection technologies are reviewed. This review is completed by arcing tests by contact opening and an arc behavior analysis. This paper also analyzes the direct current electric arc risks and damages that can occur to the mechanical safety vent pressure of the cylindrical 18650 Li-ion batteries during CID opening. In addition, an assessment of the electric arc risks related to the battery system and at CID level is performed. This paper will shed light to the electric arc phenomena and reduce the arcing risk in Li-ion batteries. The proposed solutions are a step toward the arc risk mitigation. [ABSTRACT FROM PUBLISHER]

The electrical endurance of an electromagnetic alternating current (ac) contactor can be reflected by the mass loss of its contacts during operations. This paper carries out ac contactor endurance tests in which arcing phase angles (APAs) are fixed. Contact mass losses are measured, and the electrical signals of the contactor circuit are acquired. Thus, the corresponding energies of each break process are computed. This paper investigates the relation of arcing phases, arcing energies, and mass losses of break processes, and concludes that the higher arcing energies cause greater contact mass losses. Then, this paper proposes a breaking strategy that controls the APAs to minimize and balance the contact mass losses of the three phases of an ac contactor. Therefore, the erosion on each contact is reduced and the total operation number can be increased. Compared with random breaking, the novel strategy significantly improves the electrical lifetime of the ac contactors. [ABSTRACT FROM AUTHOR]

In this paper, a compact and efficient single-phase liquid cooling system is developed for the microelectronic devices with high-power dissipation, such as the high performance servers, power amplifiers, and airborne systems. The developed system includes three major components: 1) a silicon-based hybrid microcooler; 2) a customized compact liquid-to-liquid heat exchanger; and 3) a commercial micropump. Our focus in this paper is on the efficiency improvement for the full cooling system, which includes the development of the silicon-based hybrid microcooler, and the optimization of the miniaturized heat exchanger with low pressure drop, small footprint area, and high heat exchange efficiency. The following accomplishments have been obtained through this paper. The developed microcooler combines the merits of both microjet array impingement and microchannel flow cooling technologies. The optimized heat exchanger is with about 50% of pressure drop, nearly 10% of the footprint area, and around 420% of heat transfer density of a commercial heat exchanger investigated in this paper as a benchmark. The developed system has been demonstrated with the heat dissipation capability of 350 W/cm2 on a chip of 7~\textrm mm \times 7 mm (a total power of 175 W) with a low pumping power of 0.1 W. [ABSTRACT FROM AUTHOR]