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The primary bottleneck of the stretchable mold interconnect (SMI) technology is its reliance on carrier boards. These are necessary to handle the meandered circuit during production and to ensure dimensional stability of the flexible circuit board before encapsulation. However, for all the problems it solves, it also introduces a new major problem by requiring a peeling step—which is difficult to automate. This paper aims to present some of the work that went into eliminating this problem, discussing both unsuccessful and functioning methods to tackle this conundrum and some of the experimental work that went into verifying these techniques. First, alterations to the design to simplify peeling are considered, followed by adhesive-based peeling processes and mechanical pin-based systems. Next, masking and structuring of the carrier board adhesive are considered. Finally, two carrierless methods that circumvent the problems are discussed, a two-step process—which cuts temporary support structures after partial encapsulation—and a technique whereby the frame is designed to fail in a controlled manner during the first use of the circuit, creating a carrierless process feasible for high-volume production. [ABSTRACT FROM AUTHOR]

In this paper, we present the developments of a new technology to realize 2.5-/3-D electronic circuits. The starting point is an electronic circuit embedded in a hard thermoplastic material, which is transformed into a 2.5-/3-D shape using a thermoforming process. The electronic circuit consists of stretchable copper interconnections in combination with electronic components. The circuit is produced using conventional printed circuit board process steps: a copper sheet is laminated on a thermoplastic material, such as Polycarbonate (PC) or Polyethylene Terephthalate Glycol (PET-G). The copper is structured using lithography and wet etching, and the electronic components are assembled using conductive adhesives. We investigated the use of different designs for stretchable interconnects to overcome the stretching of the electronic circuit by thermoforming it. A semispherical-shaped mold was used for this purpose where the local strain of the substrate can reach 100% with a sharp bending. It was shown that meander-shaped interconnects could accommodate the gradual deformation during the forming of the substrate either for PC and PET-G. However, at the mold’s edge, the copper-meandered tracks showed a delamination of the copper from the substrate. In the meanwhile, the electrical conductivity of the copper tracks did not show any significant variation. Another meander design based on an elliptical shape (in order to increase the length of the track) is proposed and compared with the first design. [ABSTRACT FROM PUBLISHER]

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. Initially, thinned dies are embedded in a polyimide interposer with a fine-pitch metal fanout, resulting in ultrathin chip packages (UTCPs). Next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by the introduction of an additional layer of interposer, which makes it flat at the chip edge and thus the whole package is named as flat-UTCP. In addition to that, randomness in nonfunctional package positions per panel reduces the overall yield of the whole process up to a certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of four electrically erasable programmable read-only memory dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield. [ABSTRACT FROM PUBLISHER]

In order to increase the functionality of electronic devices, while reducing the overall size and weight of the electronic chip packages, electronic chip packages can be combined into a 3-D assembly. In this field, we present a technology for stacking multiple chip packages, resulting in total volume almost equal to that of a single bare die. The technology is based on batch-processed ultrathin chip packages (UTCPs) with a fine pitch metal fan-out. Package-on-package technology enables stacking of UTCPs by vacuum lamination, followed by through-hole interconnection technology for making contacts to the metal fan-out of the embedded UTCPs within the stack. The individual chip packages can be tested before stacking. [ABSTRACT FROM AUTHOR]

The development and mechanical characterization of a novel technology for stretchable electronics is presented, which can be used for the realization of wearable textile electronics and biomedical implants. The stretchable devices consist of rigid or flexible component islands interconnected with stretchable meander-shaped copper conductors embedded in a stretchable polymer, polydemethylsiloxane. The technology uses standard printed circuit board manufacturing steps and liquid injection molding techniques to achieve a robust and reliable product. The conductors in the device are designed to accommodate strains up to 10–15%. Spin-on photo-definable polyimide as mechanical support for the stretchable interconnects and the functional flexible islands are introduced. By use of polyimide, the reliability of the stretchable interconnects, the straight interconnects on the flexible islands and the transitions between the stretchable and nonstretchable parts are improved. Long-term endurance behavior of the stretchable interconnects is studied by cyclic elongation at strain ranges of up to 20% while monitoring the electrical connectivity. It's shown that the lifetime of the polyimide supported interconnects is at least two times better compared to the nonsupported. [ABSTRACT FROM AUTHOR]

Assembly of thinned die has become common practice to meet the demand for smaller and lighter electronic products. One way to achieve this goal is to embed the thinned die into two dielectric films, which results in a flexible ultrathin chip package (UTCP). This paper describes a new UTCP process flow with microvia formation by standard UV lithography through photosensitive polyimide (PSPI). Such microvia-formation method proved to be more reliable than laser drilling techniques and simpler than a dry etching process. Since the used PSPI is self-priming, a thin layer of potassium chloride was introduced as a release layer. In the end, the polyimide encapsulation of the thinned die can be released from the carrier substrate and becomes a flexible chip package with a total thickness of around 50 \mum. Daisy-chain test dies were encapsulated inside spin-coated polyimide films. Excellent chip-to-package interconnection was demonstrated by electrical daisy chain and contact resistance measurements. Bending tests and thermal cycling tests were also performed on the daisy-chain test vehicles. Desired flexibility and reliability of UTCPs was observed. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel concept for integrating ultrathin solar cells into modules. It is conceived as a method for fabricating solar panels starting from back-contact crystalline silicon solar cells. However, compared to the current state of the art in module manufacturing for back-contact solar cells, this novel concept aims at improvements in performance, reliability, and cost through the use of an alternative encapsulant, namely silicones as opposed to ethylene vinyl acetate, an alternative deposition technology, being wet coating as opposed to dry lamination; and alternative module-level metallization techniques, as opposed to cell-level tabbing-stringing or conductive foil interconnects. The process flow is proposed, and the materials and fabrication technologies are discussed. As the durability of the module, translated into the module's lifetime, is very important in the targeted application, namely solar cell modules, modeling and reliability testing results and considerations are presented to illustrate how the experimental development process may be guided by experience and theoretical derivations. Finally, feasibility is demonstrated in some first proofs of the concept, and an outlook is given pointing out the direction for further research. [ABSTRACT FROM PUBLISHER]