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Because of the metal density requirement in the advanced CMOS processes, dummy metal fills (DMFs) are unavoidable. The DMFs degrade the performance of the on-chip inductors, especially for the ones in the microwave and millimeter-wave circuits. This paper analyzes the impact of the floating DMFs and proposes a scalable double- $\pi $ inductor model including a tunable dummy metal density factor. The metal density factor can be integrated into the process design kit and determined by the designers to pass the design rule check. The proposed model predicts the decrease in the quality factor $(Q)$ and self-resonance frequency $(f_{\mathrm {sr}})$ with the density of DMFs increasing accurately. Furthermore, a fully automatic model extraction method based on the genetic algorithm is presented, which increases the accuracy of models. Inductors with DMFs of different densities are fabricated in a standard 180-nm CMOS technology. Then, the parameters of the inductors’ models are extracted to verify the idea. The models’ calculation results are compared with the measurement results up to 67 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an improved ultrawideband open-short de-embedding methodology. In contrast to the conventional measurement-based open-short de-embedding method, the presented method is a measurement-calculation hybrid method. First, the open and short de-embedding structures are measured, and the corresponding scattering parameters are obtained. Based on this, lumped-parameter models of the open and short de-embedding structures are established. Then, the established models are modified to solve the over de-embedding problem. Finally, the modified de-embedding structure models are implemented in the scattering parameters of device test structures to achieve ultrawideband de-embedding. To verify the proposed de-embedding method, the method is applied to active devices. The results before and after de-embedding are compared under multiple bias conditions. Furthermore, the results after de-embedding based on the conventional open-short method and the proposed method are compared up to 220 GHz. These results show that using the proposed method can achieve accurate ultrawideband de-embedding up to the terahertz frequency band. [ABSTRACT FROM AUTHOR]

In this paper, a wideband model for on-chip interconnects with different shielding structures is proposed. In order to improve the performance of interconnects, solid ground, floating shields, and parallel ground shields are often employed in real applications. Based on the transmission line theory and electromagnetic wave theory, these three different shielding structures are analyzed and discussed. Also, many parasitic effects such as eddy current, skin effect, proximity effect, and substrate loss have been taken into consideration to improve the precision of the proposed model. It is shown that the simulated results of the model are in good agreement with the measured ones up to 110 GHz. The validity of the proposed model has been proven. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a V-band hybrid integrated high-gain antenna. This antenna is designed to meet the system-on-chip applications in a quad flat no-lead (QFN) package. The antenna consists of an on-chip loop radiator, a dielectric resonator (DR), and an off-chip ground plane. The on-chip radiator is fabricated to excite the DR using the standard 0.18- \mu \textm CMOS technology with a high-resistivity (HR) silicon substrate. The off-chip ground is realized by a simplified QFN die pad. Several advantages of this off-chip ground structure are discussed in this paper. The impact of the off-chip ground on the performance of the proposed DR antenna is investigated by both simulations and measurements. The DR, the off-chip ground structure, and the HR silicon substrate are simultaneously introduced in this design to augment the gain of the antenna. A measured gain of 7.8 dBi is achieved at 67 GHz with a simulated radiation efficiency of 96.7% and chip size of only $0.7 \times 1.25$ mm2. [ABSTRACT FROM PUBLISHER]

A lumped-element model for ON-chip interconnects is proposed in this paper. The effect of current return path of interconnects is analyzed. An efficient analytical parameter extraction method for the model is proposed. The inductor Lg was adopted in the shunt branch of this model to characterize the induced time-varying magnetic field. Thus, the bandwidth of the model is extended over the resonance frequency. A group of interconnects with different structures were fabricated in a 0.18- \mu \textm CMOS process to investigate the effects of current return path. The good agreement of $S$ -parameters between the model and measurements suggests that the proposed model can accurately predict the performance of interconnect in a wide frequency band up to 80 GHz, even over the resonance frequency. [ABSTRACT FROM PUBLISHER]