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Accuracy and efficiency of chip placement process play a critical role in electronic packaging technology since it can determine the success ratio and throughput of chip packaging system. In this paper, a new motional chip placement process is proposed to improve the process efficiency, where the chip is placed onto the substrate with a contact velocity. However, the moving chip is also more likely to produce position drift on the anisotropic conductive adhesive, which will result in low accuracy of chip placement process. In view of this, a three-layer model considering the effect of the chip contact velocity is presented to address the dynamic behavior of chip placement process, where the geometrical dimensions and material properties of this model are included. In addition, the mechanism of motional chip placement process is uncovered, and the effects of key factors, including chip length, adhesive viscosity, and chip contact velocity on chip motion, are analyzed. The results show that the moving chip is helpful for the efficiency of chip placement process, but it also may cause low accuracy of chip placement process. Finally, in order to select appropriate key factors, the technical criteria are discussed, and the process window for reliable motional chip placement is established and verified by experiments. [ABSTRACT FROM AUTHOR]

Continuous peeling of thin chips and flexible devices from a donor to an acceptor is critical for high-efficiency roll-to-roll (R2R) manufacturing of flexible electronics. Here, we propose an R2R conformal peeling technique for the flexible device-on-substrate electronic assembly. First, a mechanical model is established for flexible multilayer structures conformed on curved surface, such as peeling blade, and the corresponding analytical solution of the interfacial shear stress and peeling stress of the adhesive layer is given. Then, the influence of material property and geometrical size of the device (Young’s modulus of different layers and thickness of various layers), the geometric shape of peeling blade (peeling radius and conformal angle), and R2R process parameters (tension and speed of substrate) are analyzed by the theoretical model and experimental test. The peelability law of delaminating devices from the substrate is established for the conformal peeling process. Finally, the design method for a peeling blade is proposed, and the core is to determine the diameter of the peeling blade. It is proofed by the peeling experiment of multilayer electronic devices in the packaging of radio-frequency identification tags. [ABSTRACT FROM AUTHOR]

With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing. [ABSTRACT FROM AUTHOR]

Competing fracture of chip peeling and chip cracking dominates the fast, nondestructive, and reliable peeling of ultrathin silicon-based chip from polymeric substrate. Here, a competing fracture model of chip-adhesive-substrate composite structure is developed to achieve the successful chip peeling in needle ejecting process. Influences of the thickness and length of chip and layout of ejector needle on the peeling-off behavior are investigated. The theoretical prediction is found agreed well with both numerical simulation and experimental test. The process window is preliminarily determined by combining the designed experimental platform. The traditional needle ejecting process is found helpless to achieve the purpose of nondestructive peeling off for an ultrathin chip. A modified multineedle ejecting process with independently controlled ejector needles is finally proposed to improve the chip peelability. [ABSTRACT FROM AUTHOR]

Chip picking-up with vacuum sorption is a critical technology in flip-chip packaging for separating chip intactly from donor adhesive tape. With increasing length/thickness ratio of chips, the incomplete separation affects the success rate of this process, even leads to the failure of chips. Here, we present a theoretical model with a bisection algorithm to calculate the effective size of tape that contributes to the crack growth, and introduce an energy release rate and pick-up force to evaluate the ability of thin chip picking-up. The finite-element method with a virtual crack-closure technique is constructed to validate the established process model. The effects of the type of pick-up head, length of chip, thickness, and material of tape on chip picking-up process are also revealed to improve the ability to propagate a crack in the adhesive layer. Furthermore, the crack propagation in the adhesive layer with increasing pick-up displacement is predicted to determine the critical value of the thin chip complete separation from compliant tape. These results suggest that the thinner and more compliant tape should be adopted in the chip picking-up process. [ABSTRACT FROM PUBLISHER]

Flip chip packaging as a mainstream packaging interconnect technology has proliferated rapidly within the last decade or so. With the applications of high-performance chip, its thickness and size have been much thinner and bigger, which is challenging the current assembly technique, especially for the reliable peeling of ultrathin die from the wafer due to its vulnerability and flexibility. Here, we present some significant analytical formulas to estimate die cracking stress and peeling energy in die peeling process. The effects of two factors, including peeling cracking propagation and ejecting needle configuration, are investigated using a fracture mechanics framework. Meanwhile, all analytical predictions have been verified via finite element modeling with virtual crack technique. Theoretical results have shown that die cracking stress could be effectively reduced, but it rarely works to improve peeling energy when more needles are embedded below the adhesive tape. In particular, the essence of the technique with the multineedle is discussed, compared with the normal single-needle technique, which can be used to guide the design of ultrathin die peeling process. [ABSTRACT FROM AUTHOR]

The efficient pick-up of thin/ultrathin integrated circuit chip from the wafer is one of the key techniques in advanced microelectronic packaging, whose success rates are determined by the peeling-off of chip from the adhesive tapes. Analytical models for estimating the effects on process parameters represent important design tools. Here, solutions for adhesive stresses and mixed-mode peeling are presented in chip-adhesive-substrate structure based on mixed boundary conditions, in which the geometrical dimensions and material properties of this three-layer system are included. Analytical expressions are defined in terms of structural parameters and several integration constants, which can be obtained by a given system of linear equations. These models agree well with finite element models with virtual crack-closure technique. In particular, the mechanism of tunable mode peeling is uncovered, and the technological limit of normal single ejecting needle is discussed. [ABSTRACT FROM PUBLISHER]

The IC chip ejecting and pick-up process in electronic assembly plays a critical role in advanced packaging since the success ratio and productivity are determined by the delamination of thin chips from the underlying substrate. For a chip-on-substrate structure subjected to a transverse concentrated load resulting from the ejecting needle, a competing relationship between chip peeling-off and chip cracking is discovered from the perspective of integral structure. A competing index, \Gamma, is defined to characterize the competing fracture behavior between cracking and peeling-off, and the competing fracture mechanism is then uncovered fundamentally. Based on the index, the effects of chip geometry on competing behavior are investigated using the virtual crack-closure technique with dummy nodes. Critical thickness and length, which separate chip peeling-off and cracking modes, are found and they represent the extremity of successful pick-up process. The critical values are determined by critical competing index, \Gamma=\Gammac. The competing mechanism uncovered applies to general pick-up process with various chip sizes and materials. The critical sizes and the method of evaluating critical values are meaningful for chip profile design, optimization of pick-up process, and propelling new designs of electronic assembly process, especially for thin chips. [ABSTRACT FROM PUBLISHER]

The roll-to-roll (R2R) processing plays an increasingly important role in the high-throughput fabrication of flexible electronics. This paper highlights the dramatic influence of material properties, geometrical dimensions of film-on-substrate structure, process temperatures, and web tension of the R2R processing. A co-optimization approach has been presented for the R2R processing, and all the design and process parameters are to be simultaneously optimized to reduce the interfacial residual stress. First, the misfit strain between the thin film and the substrate is established based on the process parameters. The temperature-dependent properties are involved in polymer/rubber substrate. Nonlinear phenomena are discovered when the process temperatures and the web tension are involved in substrate together. Then, the interfacial shear and peeling stresses resulted from R2R processing are derived in analytical model based on the generalized plane strain theory. The interfacial stresses are related with process temperatures, material properties, and structural dimensions. Finally, a multivariable optimization model is established to compensate the misfit strain. The results imply that device structures and process parameters are correlated phenomena and therefore should be simultaneously optimized in the R2R processing of flexible electronics. [ABSTRACT FROM PUBLISHER]