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For system-on-chips (SoC) using nanometer technologies, buses and long interconnects are susceptible to crosstalk defects that may lead to functional and timing failures. Testing for crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage of existing tests and facilitate the development of new crosstalk test methodologies, effective crosstalk-defect coverage-analysis techniques are needed. In this paper, we present an efficient high-level crosstalk-defect simulation methodology for interconnects dominated by capacitive coupling effects. A novel coupling defect-simulation model was developed and implemented in hardware description languages. The high-level crosstalk-defect simulation methodology was examined by SPICE simulations. Experimental results show the crosstalk defect simulation methodology efficiently provides high-fidelity defect-coverage results. The proposed methodology enables fast exploration and evaluation of different tests, leading to high-quality, low-cost manufacturing tests for crosstalk-induced ac failures. [ABSTRACT FROM AUTHOR]

With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. traditionally in static noise analysis, drivers' holding resistances are precharacterized without considering the potential Impact of crosstalk noise. However, crosstalk induced voltage fluctuation strongly affects the: behavior of nonlinear drivers. When facing different coupling interconnects and hence crosstalk noise, a driver's holding resistance can change dramatically. In nanometer circuits, this substantial variation of nonlinear driven cannot be totally Ignored. To achieve high-quality in noise estimation yet maintain the efficiency of linear circuit model, we propose a novel interconnect coupling-aware driver modeling method. Eased on layout-extracted interconnect parameters and precharacterized driver models, an effective holding resistance is calculated to capture the impact of the nonlinear driver. Multiple aggressors with synchronous and asynchronous switching activities are also considered. The proposed method is simple, efficient, and enables on-the-fly calculation of the effective holding resistance. Experiments show that with negligible computation overhead, the coupling-aware driver modeling methodology can significantly improve the quality of static noise analysis. [ABSTRACT FROM AUTHOR]

Rapid growth in the complexity of system-on-chips is being accompanied by increasing volume and diversity of on-chip communication traffic, which in turn, is driving the development of advanced system-level communication architectures. While these architectures have the potential to improve system performance, they pose significant new challenges to the system designer, owing to the complex design space defined by the availability of numerous network topologies, communication protocols, and mapping alternatives for system communications. In this paper, we address the problem of mapping a system's communication requirements to a given communication architecture template. We illustrate the nature of the communication architecture design space, and describe an exploration methodology that uses efficient algorithms to help automate the process of mapping the system communications to the selected template. In addition, we demonstrate the importance of simultaneously optimizing the on-chip communication protocols in order to maximize system performance. Experiments conducted on example systems, including a cell forwarding unit of an ATM switch, indicate that the proposed techniques aid in automatically constructing communication architectures that have high performance. For the systems we considered, the solutions generated using our methodology had 53% superior performance (on average), over those based on conventional architectures and mapping approaches. The algorithms used in the proposed methodology are computationally efficient, and scale well with increasing communication architecture complexity. [ABSTRACT FROM AUTHOR]

The ability to efficiently and accurately estimate battery life under different design choices at the system level is an important aid in designing battery-efficient systems. Recently developed battery models help by estimating battery life under given profiles of the battery discharge current over time. However, existing techniques for energy (or average power) estimation do not provide sufficient information (such as time profiles of system power consumption) to drive battery-life estimation. Techniques that are capable of generating such profiles often lack the efficiency required to support exploration at the system level. In this paper, we describe techniques for efficient generation of system-level power profiles, for use in a battery-life estimation framework. Our power profiling technique allows a designer to experiment with: 1) the mapping of system tasks to a set of architectural components and 2) the mapping of system communications to a specified communication architecture, and efficiently generate system power profiles for each alternative. The resulting profiles can then be analyzed using existing battery models to estimate battery lifetime and capacity. Extensive experiments conducted on an IEEE 802.11 MAC processor design demonstrate that our power profiler offers orders of magnitude improvement in runtimes over state-of-the-art cosimulation-based power estimation techniques, while suffering minimal loss of accuracy (average profiling error was 3.8%). [ABSTRACT FROM AUTHOR]

In this paper, we present a methodology for the design of high-performance system-on-chip communication architectures. The approach is based on the addition of a layer of circuitry called the communication architecture tuner (CAT) layer around an existing communication architecture topology. The added layer provides a system with the capability of adapting to runtime variability in the communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower communication latencies. The CAT associated with each component monitors its internal state, analyzes the communication transactions it generates, and "predicts" the relative importance of the transactions in terms of their impact on system-level performance metrics. It then configures the protocol parameters of the underlying communication architecture (e.g., priorities, burst modes, etc.) to best suit the system's changing communication needs. We illustrate the issues and tradeoffs involved in the design of CAT-based communication architectures, and present algorithms that automate the key steps. Experiments with example systems indicate that performance metrics (e.g., number of missed deadlines, average processing time) for systems with CAT-based communication architectures are significantly (sometimes over an order of magnitude) better than those with conventional communication architectures. [ABSTRACT FROM AUTHOR]

This paper introduces hot potato behavioral synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registers and the number of interconnects, are significantly reduced. Moreover, we demonstrate how hot potato techniques can be effectively used during behavioral synthesis to minimize the partial scan overhead to make the synthesized design testable. [ABSTRACT FROM AUTHOR]

This paper proposes a novel circuit design methodology, called common-case computation (CCC)-based design, and new design automation algorithms for optimizing energy consumption and performance. The proposed techniques are applicable in conjunction with any high-level design methodology, where a structural register-transfer level (RTL) description and its corresponding scheduled behavioral (cycle-accurate functional) description are available. It is a well-known fact that in behavioral descriptions of hardware circuits (and also in software programs), a small set of computations often account for most of the computational complexity. However, in the hardware implementations (structural RTL or lower level), the common cases and the remaining computations are typically treated alike. This paper shows that identifying and exploiting common cases during the design process can lead to implementations that are much more efficient in terms of energy consumption and performance. We propose a new high-level design methodology with the following steps: 1) extraction of common-case detection and execution behaviors from the scheduled description; 2) simplification of the common-case behaviors in a stand-alone manner; 3) synthesis of common-case detection circuits and common-case execution circuits from the common-case behaviors; and 4) composing the original design with the common-case circuits to result in an optimized design. We demonstrate that the optimized designs reduce energy consumption by up to 59.8%, and simultaneously improve performance by up to 76.6%, compared with designs derived without special regard for common cases. The simultaneous improvements in energy and performance result in energy-delay product improvements of up to 90.6%. [ABSTRACT FROM AUTHOR]

Presents a study which proposed a system-level performance analysis technique to support the design of custom communication architectures for system-on-chip integrated circuits. Effect of alternative communication architectures on system performance; High-performance system implementation; Effect of customizing bus protocols on system performance.

Introduces a software-based self-testing methodology for processors which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. Challenges facing logic built-in self-test (BIST); Experiences with applying logic BIST to processors; Description of the proposed software-based self-test methodology targeting structural faults; Application of the software-based self-test methodology.

Presents the SOCET technique for testing core-based system-chip. Other methods for system-chip testing; Method for obtaining core transparency; Results of the application of the system.

Presents information on a study which discussed a power management technique that redesigns control logic to reconfigure the existing data path components. Details on power consumption in complementary metal oxide semiconductor circuits; Characteristics of control-flow intensive designs of circuits; Effect of redesigning control logic to data path signals; Results and conclusions.

Presents a design-for-low-power techniques for register-transfer level (RTL) controller/data path circuits. Impact of glitch generation and propagation of RTL circuit; Description of the glitch reduction techniques; Information on the reduction of register power consumption by gating clock inputs to registers.

Investigates the possibility of repositioning flip-flops (FFs) so that in the modified circuit, every circuit minimum feedback vertex set (MFVS) gate drives one FF that can be scanned. Information on resynthesis and retiming of circuits; Conditions where legal retiming can produce FF repositioning.

Studies the effect of the controller redesign technique on the testability of sequential circuits composed of controllers and data paths. Introduction to scan-based design-for-testability (DFT) techniques; Experimental results; Conclusions.

Presents information on a study concerning the nonscan design-for-testability (DFT) techniques to register-transfer (RT)-level data path sequential circuits. Illustration of scan and non-scan DFT of RT-level paths; Cost-effective DFT approach; Reconvergent regions introduced while adding nonscan DFT.