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This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits. [ABSTRACT FROM PUBLISHER]

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for the efficient modeling of substrate noise coupling. A closed-form Green's function for nonuniformly doped substrates is employed with the correct singular characteristics. A novel global surface impedance matrix scheme is introduced to efficiently model nonuniformly doped wells, channel stop implants, and buried layers. Layout, device, and netlist extractors are developed so as to integrate our boundary element method (BEM) solver with commercial layout and circuit simulation tools. [ABSTRACT FROM AUTHOR]

Presents an electromigration reliability diagnosis tool (iTEM) for complementary metal oxide semiconductor (CMOS) very-large scale integration (VLSI) circuits. Temperature effect on electromigration reliability; Block diagram of iTEM; Results of electrothermal timing simulation.