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Advances in multiple-valued logic (MVL) have been inspired, in large part, by advances in integrated circuit technology. Multiple-valued logic has matured to the point where four-valued logic is now part of commercially available VLSI IC's. Besides reduction in chip area, MVL offers other benefits such as the potential for circuit test. This paper describes the historical and technical background of MVL, and areas of present and future application. It is intended, as well, to serve as a tutorial for the nonspecialist.

Nine basic fuzzy logic circuits employing p-ch and n-ch current mirrors are presented, and the fuzzy information processing hardware system design at a low cost with only one kind of master slice (semicustom fuzzy logic IC) is described. The fuzzy logic circuits presented here will be indispensable for a "fuzzy computer" in the near future.

A new method to implement multiple-valued logic in large scale integrated circuits is introduced. The data are represented by discrete amounts of charge in a charge-coupled device. In this paper the design principles and realizations in four-valued logic of a minimum and maximum circuit, a complement circuit, a literal a successor, and an adder are presented. Also, the designs of a binary-to-quaternary converter and vice versa are discussed. Charge-coupled devices offer low-power consumption, high-packing density, and the possibility to perform MOST-IC compatible multiple-valued logic in any arbitrary radix.

The density of integrated circuits has improved in the last 15 years by 4 to 5 orders of magnitude. This paper discusses four primary computer technology areas that have helped bring about this advance and which have significantly changed the nature of computer components: FET logic, FET memory, bipolar logic, and bipolar memory. Projections are made for future trends in these technologies.

Logic-in-memory (LIM) organization allows central processor functions of computing systems to be combined with memory in regular arrays. The cells of these arrays can themselves be constructed regularly and economically using similar two-level emitter-function logic (EFL) structures. The structure is a development of current-mode logic and it permits the large-scale integration (LSI) realization of three levels of logic with similar silicon area and power dissipation to a single conventional emitter-coupled logic (ECL) gate. It also permits the realization of a D latch in a single structure. The capability of the structure is demonstrated in examples of LIM data transfer and sorting arrays.

A conservative logic element (CLE) is a multiple-output logic element whose weight of an input vector is equal to that of the corresponding output vector, and is a generalized model of magnetic bubble logic elements, fluid logic elements, and so on. This paper considers the problem of realizing arbitrary 3-input 3-output conservative logic elements (3-3 CLC's) by cascade connections of 3-input 3-output CLE's called "primitives." It is shown that the necessary and sufficient number of different primitives to realize an arbitrary 3-3 CLC is three in the case when the crossovers of lines are permitted, and four in the case when the crossovers of lines are not permitted.

Parallel counters are multiple-input circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementations are compared to their binary full adder network counter equivalents. This logic form was selected because of the increasing importance of implementing state-of-the-art digital signal processing systems in large-scale-integrated (LSI) circuit form. LSI circuit designs are, in general, limited by the number of metal signal and power lines that must be placed upon the chip's surface, not by the number of active and passive devices used. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over 50-percent savings in the total number of signal variables required to implement the parallel counter results. Also, with the circuits we describe here, approximately 50 percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters. These savings are attainable with a modest tradeoff in speed and power.

This paper is concerned with the realization of logic functions by using two-input magnetic bubble logic elements. A magnetic bubble logic element is the multiple-output logic element whose number of ``1'' 's of the output is equal to that of corresponding input, and fanout of each output terminal of the element is restricted to one. In order to realize some functions, it is necessary to use the generators which correspond to constant-supplying elements. First, the number of generators which are necessary and sufficient to realize an arbitrary functions is obtained for a given set of elements. In particular, it is shown that an arbitrary function can be realized by using I B elements and at most two generators. Since the I B element is a universal element in the above sense and is considered to be rather easily realized by magnetic bubble interactions, the I B logic circuits are mainly discussed. The I B minimum circuit defined here is a circuit which consists of minimum number of generators and minimum number of I B elements. In the last half of this paper, it is shown that the minimum circuits of most functions have the characteristic circuit structure called ``1-4 form.''

A method of realizing arbitrary combinational switching functions with multiplexers is derived. These circuits are divided in two classes where the first allows only uncomplemented variables as control inputs and the second has unrestricted inputs. The selected inputs to each multiplexer in the first class of circuits (tree circuits) are shown to be residue functions of the output function. Using this fact, it is demonstrated that many functional properties simplify realization procedures.

The emitter function iogic (EFL) structure is a bipolar integratable circuit suitable for large-scale-integration (LSI). The structure is a development of current-mode logic and it permits the LSI realization of complex logic functions with similar silicon area and power dissipation to a single conventional ECL gate. In order to use the structure in logic design, some of its properties are developed and a logic design technique is given with examples.

A differential current-switching circuit configuration is proposed for implementing threshold logic, and a first-order statistical analysis of the configuration is described. The configuration is intended for use within functional digital integrated circuits. It can be realized in a form that is fully compatible with conventional emitter-coupled logic (ECL).

When we design networks with NOR or NAND gates which are implemented with bipolar and MOS transistors, wired logic is usually allowed. The usage of wired logic reduces the network cost and possibly improves the speed because of shorter delays on wired logic than on a gate. Typical logic functions performed by wired logic are AND and OR, which are called wired-AND and wired-OR, respectively. Properties of networks with NOR gates and wired-AND (or wired-OR) are discussed. Some of these properties are used in developing synthesis procedures of optimum networks by the integer programming logic design method. For all three-variable functions, the optimum networks with NOR gates and wired-OR's, designed by this synthesis approach, are shown.

An algebraic system for designing multivalued (four-level) I2L circuits is presented here. It was necessary to develop this system because the use of existing multivalued logic formalisms does not result in efficient I2L circuits. The close relationship between the algebra and the integrated circuits is stressed throughout the paper.

A synthesis procedure must be based upon some cost function or functions. In many systems this cost function is associated with performance. But the usual cost function associated with switching circuits is associated with the cost of realization. Inspection of switching circuits indicates that many switching circuits are not used efficiently and that a measure of component efficiency is the ratio of data rate to component capacity or switching speed. The multiplex logic circuits are designed so that the above efficiency can be improved and as a consequence the number of circuits required can be substantially reduced. Special auxiliary circuits are required. The complexity of these auxiliary circuits is mentioned but not treated.

—Four-phase MOS circuits exhibit many peculiar features not observed in other families of logic circuits. In this paper, a mathematical model which characterizes the circuits is presented for logic simulation. It is shown that this model enables us to develop a computer program which can rapidly and efficiently verify and evaluate the logic design of the circuits.

An eight-transistor static logic gate has been designed, which generates the functions OR, NOR, and, nand, xor, and XNOR of two logic variables, under the dynamic control of two programming variables. In addition to its versatility as a building block, the dynamic programmability of the gate makes it a powerful tool for the efficient design of complex digital networks.

By using two magnetic-bubble positions per bit it is possible to develop simple logical circuits which display essentially unlimited fan-in and fan-out. Systems of these circuits can be organized such that they conserve bubbles. Pipelining methods can be employed to enhance the throughput.

This paper reviews the impact of solid-state technology on the design and implementation of analog computers. Eight figures show the effects of transistors and medium-scale integrated circuits in the various phases of computer development. Basically, the use of integrated circuits is divided into two areas: logic and linear. Logic, or digital, circuits have been used for the control and address selection in the analog computer. Contrary to the author's claim that electromechanical devices used in the 1958 vintage machines were reliable with proper maintenance, transistor control logic was introduced specifically to improve the reliability and speed of the analog computer. (I do not believe that anyone who had to maintain stepping switches would disagree with me.) The introduction of patchable logic combined with the transistor control logic was a big step forward in increasing flexibility for the computer operator. As integrated circuits became practical from the viewpoint of cost per function, the control and patchable logic changed over to integrated circuits with additional features and flexibility.

The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder.

An eight-transistor static logic gate has been designed, which generates the functions OR, NOR, AND, NAND, XOR, and XNOR of two logic variables, under the dynamic control of two programming variables. In addition to its versatility as a building block, the dynamic programmability of the gate makes it a powerful tool for the efficient design of complex digital networks.