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This paper presents a unique methodology to calculate the filtering capacitances of the OpAmp already reported in the literature. The methodology aims to show that there is an optimal solution that can be used to increase the electromagnetic interference (EMI) immunity of any OpAmp for a wide range of frequencies. By using this proposed methodology, an OpAmp structure that reduces the EMI effect is designed in standard 0.18\ \mu \textm mixed-mode CMOS technology. Detailed mathematical analyses and simulation results are presented and discussed. Simulation results show that the maximum EMI-induced offset voltage in the frequency range from 1 MHz to 1 GHz for the OpAmp is 4.4 mV. In contrast, the standard Miller OpAmp exhibits a maximum EMI-induced offset voltage of 92.4 mV under the same operating conditions. [ABSTRACT FROM PUBLISHER]

The  power distribution network (PDN) of a high-speed printed circuit board requires a high-performance power supply. The total equivalent inductance above the top ground plane is an important part of PDN design and is regarded as Labove. In this paper, an inductance library for different structures of capacitor connections and capacitor sizes has been built, which is essential for PDN design. computer simulation technology (CST) and partial element equivalent circuit method are applied to obtain the shorted pattern design curves at various design data. The shorted pattern design curve means the total equivalent inductance varies with the distance between pad and ground plane. In addition, an approximate shorted model is established for a decoupling capacitor-mounted model, which will be convenient for us to get the inductance of Labove. In this paper, the design curve provides an intuitive guideline in designing PDN and facilitates the industry to choose what they want with consideration of the inductance, space, via numbers, etc. [ABSTRACT FROM AUTHOR]

This paper presents circuit design methodologies to enhance the electromagnetic immunity of an output-capacitor-free low-dropout (LDO) regulator. To evaluate the noise performance of an LDO regulator in the small-signal domain, power-supply rejection (PSR) is used. We optimize a bandgap reference circuit for optimum dc PSR, and propose a capacitor cancelation technique circuit for bandwidth compensation, and a low-noise biasing circuit for immunity enhancement in the bias circuit. For large-signal, transient performance enhancement, we suggest using a unity-gain amplifier to minimize the voltage difference of the differential inputs of the error amplifier, and an auxiliary N-channel metal oxide semiconductor (NMOS) pass transistor was used to maintain a stable gate voltage in the pass transistor. The effectiveness of the design methodologies proposed in this paper is verified using circuit simulations using an LDO regulator designed by 0.18-$\mu$m CMOS process. When sine and pulse signals are applied to the input, the worst dc offset variations were enhanced from 36% to 16% and from 31.7% to 9.7%, respectively, as compared with those of the conventional LDO. We evaluated the noise performance versus the conducted electromagnetic interference generated by the dc–dc converter; the noise reduction level was significantly improved. [ABSTRACT FROM PUBLISHER]

An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements. [ABSTRACT FROM AUTHOR]

The measurement of overvoltage in a power distribution network is the basis for detecting lightning-induced overvoltage. This paper proposes a lightning-induced overvoltage monitoring device using a ceramic capacitor insulator that is powered by the line and employs wireless transmission. The sensing principle of the monitoring device, the power-supply principle of ceramic capacitor voltage division, and power electronic switching device, as well as the principle of signal acquisition and wireless transmission are expounded. The power self-acquisition module can take out 2 W of power from a single line to meet the requirements of the monitoring device. The monitoring system was tested with a 10 kV test platform. The transient response characteristics, the power self-acquisition capability, and the linearity of the sensor were obtained. The overall performance of the monitoring device was also tested. The operation status of the monitoring device on the distribution line and the monitored overvoltage signal showed that the device can capture lightning-induced overvoltage signals and be used in a distribution network system. [ABSTRACT FROM AUTHOR]

In this paper, the plane-pair partial element equivalent circuit method coupled with the field equivalence principle is developed and applied to calculate the radiated fields of multilayer power planes. The proposed method can be used to solve near-field and far-field radiation problems for multilayer parallel-plane structures with decoupling capacitors. The proposed method is validated by full-wave simulation and experiment. In addition, the proposed method achieves ten times higher computational efficiency than the full-wave simulation. [ABSTRACT FROM AUTHOR]

This paper presents two electromagnetic interference (EMI) resisting current mirror topologies that use a linearization technique to filter out the EMI without producing any offset at the output. A proposed current mirror illustrating the linearization concept is implemented in standard $\text{0.18}\;\mu \text{m}$ mixed-mode CMOS technology. Measurement results show that for a frequency range of 10 kHz–10 MHz, the EMI-induced offset current produced by the proposed current mirror is negligible as compared to the traditional current mirror. [ABSTRACT FROM AUTHOR]

Parasitic inductance limits the high-frequency performance of surface mount capacitors in a shunt filtering configuration. This paper introduces a new compact design for cancelling this parasitic inductance that makes use of magnetic coupling between vias, as well as between coplanar traces. This design is intended for use on PCBs with more than two layers, and is an extension of the designs presented in the recent paper by the authors, “Parasitic Inductance Cancellation for Surface Mount Shunt Capacitor Filters.” Implementations of the new design are shown to exhibit similar filtering performance to comparable implementations of previously published designs, while requiring nearly 40% less board area. Additionally, implementations of the design are demonstrated to be effective in the practical situation of filtering the noise due to crosstalk on a four-layer board. [ABSTRACT FROM AUTHOR]

Power distribution network (PDN) design in high speed digital systems is a critical challenge for system performance. Common design methodologies refer to guidelines and engineering best practices while using simulations to evaluate the design. If the relation between the design choices and the performance parameters is known, the engineering is simpler. A lumped circuit model that relates physics and design geometry was proposed in an earlier study for modeling practical printed circuit board (PCB) PDN designs. In this paper, the lumped circuit model proposed earlier is used to develop a well-defined relation between the design geometry, the model elements, and the PDN impedance response features. The PDN impedance is simplified and broken down into common features for all PCB PDNs. These features are mapped to the model elements using sensitivity analysis and consequently to design geometry. The physics behind the relation between the response and geometry is reinforced with the current paths in different frequency ranges and generalized to common PDN designs on multilayer PCBs that use area fills for the power net. [ABSTRACT FROM PUBLISHER]

Passive components, in particular capacitors and coupled inductors, are the most important parts of electromagnetic interference (EMI) filters. The parasitic elements of these components and the impact of temperature on their frequency behavior are very significant and should not be neglected; these unwanted effects have a major impact on EMI filter performances. In this paper, characterization test-benches and modeling methods of capacitor and coupled-inductor impedances via measurements are presented. The aim of this study is to propose relatively simple models in order to estimate, by simulation, the frequency behavior of EMI filters in a wide range of temperature. The new models are simulated for several values of temperature and the obtained results are compared to the experimental measurements in the frequency domain. The developed models are then translated to VHDL-AMS language for easy implementation in most electrical simulation software. [ABSTRACT FROM AUTHOR]

Proper power integrity (PI) analysis is required for printed circuit board (PCB) power distribution network (PDN) design. Top-layer interconnect inductance for PI has always been a vital concern for high-speed industry. Developing a simple physics-based equivalent circuit model for critical structures is essential for understanding the physics of the system and for intelligent designs. In this paper, a physics-based model size reduction (PMSR) method is applied to get the equivalent circuit model for the above-ground geometries. The extracted physics-based models are also based on the partial element equivalent circuit (PEEC) method, and can be used in analyzing the structure in its parts. By applying PMSR method, a physics-based equivalent circuit model can be proposed and this circuit model is related to the geometric features of the design. In this way, PMSR method can provide an intuitive guideline in designing PCB and reducing above inductances, therefore, a low-ripple dc voltage can be delivered through PDN. Taking advantage of PEEC and PMSR methods, the top-layer inductances of three different geometries are calculated and the physics-based circuit models are obtained, respectively. [ABSTRACT FROM AUTHOR]

The carrier frequency harmonics and significant high-frequency energy of electromagnetic interference (EMI) produced is a major concern in pulse width modulation (PWM) circuit. This paper proposes a chaotic PWM generator for the reduction of EMI. The chaotic CMOS circuit presented is based on a stroboscopic map to realize the chaotic sequence generator, and then, this chaotic frequency generator is used to replace the constant-frequency generator. The main components of the chaotic PWM circuit are chaotic sequence generator for the chaotic triangle waveforms, the chaotic frequency modulation circuit based on one chip. The chaotic PWM generator is fabricated by a 0.35 μ m standard CMOS process. The energy peak of EMC experiment values are all within the limit of CISPR 22. The peak EMI reduction of the proposed chaotic PWM is 12.85 dB. The experiments show the effectiveness of the proposed CMOS chaotic PWM in reducing EMI. [ABSTRACT FROM PUBLISHER]

This paper proposes an equivalent circuit model of a multilayer ceramic capacitor (MLCC), in which the impedance characteristics of an MLCC could be predicted at design stage before fabrication and measurement. An MLCC can be divided into three regions: end, overlap, and nonoverlap regions depending on the spatial structure of the plates, and the parameters, such as R, L, G, and C are calculated in each region analytically using partial inductance of rectangular plates or/and multiconductor transmission line theory. The measured and EM-simulated impedance of an MLCC coincides to the calculated impedance from the proposed model quite nice over almost the whole frequency range of interests, which proves the validness of the proposed model. Since calculation time is actually nil using the proposed model, compared to the time using the EM simulation, the model can be very useful when one needs to design an MLCC, especially when one needs a lot of iterations to obtain the final design target of an MLCC. [ABSTRACT FROM PUBLISHER]

There are many different definitions of the risetime of a transient waveform. In the context of high-altitude electromagnetic pulse (HEMP) standards, the 10–90% risetime of an idealized double exponential waveform has been defined and used for many decades. However, such a risetime definition is not strictly applicable to the transient voltage out of a pulse generator, since no practical switch can close in zero time. In this paper, we discuss various definitions and their applicability. More importantly, pulse power technology has evolved over five decades and the achievable risetimes have come down from 10s of nanoseconds to 10s of picoseconds. As a corollary, the highest achievable voltage gradient has been going upwards of 10^15 V/s. In this paper, we review the definitions of risetime, and trace the evolution of technology and HEMP Standards, exclusively for the E1 environments. [ABSTRACT FROM AUTHOR]

This paper shows an approach for the broad-band modeling of passive power-supply filter structures, which may be applied to the virtual filter design. The most important advantage of this technique is the possibility of considering the parasitic and functional behavior of a power-supply filter in the same simulation. The approach provides a 3-D model of the filter structure based on a differential field solver. Moreover, the passive components are approximated by combined behavioral-physical 3-D models, which allow the simulation of this structure and the physical volumetric modeling of the current distribution in the components. Thus, the functional behavior of the filter is modeled taking into account all the high-frequency effects (equivalent serial inductance, equivalent serial resistance, parasitic capacitances, punch-grid issues, couplings between components, couplings between interconnections, losses in the plastic environment, etc.). This paper provides a validation of the approach by measurements of a simplified hardware sample and of an industrial filter sample as well. [ABSTRACT FROM AUTHOR]

Near-field electromagnetic couplings between an electromagnetic interference (EMI) filter and the main circuit have serious impacts on EMI performance of a power converter. In order to improve the EMI performance, it is necessary to analyze the near-field coupling effects of power converters. In this paper, a Boost power factor correction converter and a CL EMI filter are used for analysis of near-field inductive couplings. This paper presents a method to extract parasitic inductive coupling parameters by means of network gain measurement. With the extracted coupling parameters, it builds up a circuit model for the converter. The model is then used to analyze the effects of inductive couplings between the EMI filter and the main circuit on EMI performance of the converter. The analysis shows that the inductive couplings of the filter choke are harmful to a low-frequency differential-mode (DM) EMI, whereas the inductive couplings of the filter capacitor are harmful to a high-frequency DM EMI. [ABSTRACT FROM AUTHOR]

The paper treats the effect of layout on the electromagnetic interference (EMI) of buck converters. An optimized layout design for dc-dc synchronous buck converter is proposed for EMI reduction. Six different layout versions are analyzed with respect to loop area, loop inductance, radiating dipole moments, and far-field radiation. Optimizations are done with respect to field-effect transistor (FET), decoupling capacitor and via placement. Passive full-wave simulations are used to estimate and verify the loop inductance and far-field emissions. Those are compared with measurements. A gigahertz transverse electromagnetic (GTEM) cell is used to quantify the dipole moments in the printed circuit board (PCB) for estimating the far field and comparing to measurement. [ABSTRACT FROM PUBLISHER]

This paper illustrates effects of board edge termination related to development of either voltage or return plane bounce exceeding operational margin levels of digital components at multiple locations within a printed circuit board (PCB). We study an actual problem encountered by design engineers using a worse-case configuration. This paper also explains how power and/or return bounce is developed. Lack of optimal plane termination at the physical edges of a PCB will exacerbate plane bounce. In addition, a solution that prevents this problem is provided in Section VIII. [ABSTRACT FROM PUBLISHER]

The decoupling of modern printed circuit boards introduces a very complex task. Powerful stochastic optimizers are usually used to determine values and positions of decoupling capacitors on the board. The number of capacitors used has to be determined a priori by the user which brings problems with convergence of the optimization process or can lead to a waste of resources when the noises are to be attenuated to a certain level. In this paper, an approach based on the combination of time-domain contour integral method and optimization with variable number of dimensions is introduced. The optimizer works with models having variable dimensions and searches for the optimal one. The approach is tested on two example power circuit boards with various noise attenuation limits and constraints on capacitor positions and values. [ABSTRACT FROM AUTHOR]

This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system's response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power–time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction's microscopic geometry, material information, defect location, or melting temperature. [ABSTRACT FROM AUTHOR]

The saturation of a common-mode (CM) choke is a practical problem in the electromagnetic interference filter application. As an important factor of the CM choke saturation, the self-resonance of the CM path is analyzed based on the low-frequency CM model of the variable-frequency drive system. Combining the analysis and the conducted emission test results of the system, the main cause of the CM choke saturation in our experiment is studied. Meanwhile, a novel online impedance measurement method is proposed to observe the saturation effect of the CM choke. To eliminate the saturation effect, a new method is proposed in this paper. A damping resistor is connected in parallel with Y capacitor of an electromagnetic interference filter to suppress the self-resonance. Through comparing the experimental results of the original filter and the improved filter, the effectiveness of the resonance suppression method is validated and the saturation of the CM choke is prevented. [ABSTRACT FROM AUTHOR]

Designing of low-cost and more compact electromagnetic interference (EMI) filters must be achieved by considering intercomponent coupling. Actually, magnetic coupling, arising from the proximity of the components constituting the filter, has a major influence on the filter performance. The aim of this paper is to present a methodology for filter design, which takes into account intercomponent coupling and, therefore, can predict filter attenuation very accurately, whatever the structure and the topology of the filter may be. [ABSTRACT FROM AUTHOR]

Electromagnetic interference (EMI) has drawn great attention in recent years. In this particular case, it is generated by the three-phase inverters in power electronics applications due to the power devices turningonandoffat high frequency. In this paper, in order to alleviate such EMI noise, a high-frequency common-mode (CM) equivalent model is developed, which leverages the effect of parasitic parameters. Meanwhile, in order to eliminate the effect of the parasitic capacitance between the phase node and ground, which is the cause of main CM noise propagation, a coupled inductor connected with a capacitor circuit, which is equivalent to a negative capacitance is proposed. The parameter calculation for the passive negative capacitance circuit is given in detail. The experimental results demonstrated the effectiveness of the circuitry structure and its ability to reduce CM noise. [ABSTRACT FROM AUTHOR]

The objective of this paper is to present a methodology for identifying the current flow in the capacitors of a multiphase buck converter by synchronously measuring the capacitor currents. A multiphase buck converter uses multiple parallel buck converters with different switching times to source a large amount of current. Currents in the primary capacitors of a multiphase buck converter are drawn by all phases of the converter; however, the phases switch asynchronously. Synchronizing to the switching of a specific phase reveals how the current from that phase is distributed among the capacitors throughout a circuit board. The proposed measurement method is illustrated by comparing an initial printed circuit board design to a new design to show the effect of better capacitor placement and the addition of a ground plane. The new design confines the phase currents to the capacitors close to the field effect transistors of the specific phase. [ABSTRACT FROM AUTHOR]

Parasitic mutual inductance between the input and output loops of a shunt capacitor filter limits the attenuation obtainable at high frequencies. This paper presents compact designs for integrated cancellation coils for surface mount shunt capacitor filters that enable these filters to be effective from megahertz to gigahertz frequencies. Computer inductance extraction tools are used to optimize the filter performance. Experiments are performed to validate the designs. A lumped element model of the filter describes the secondary parasitics that affect the performance and ultimately determine the bandwidth of the filter. [ABSTRACT FROM PUBLISHER]

In this paper a new procedure is presented for predicting the effect of electromagnetic interference (EMI) on the dc shift, harmonic, and intermodulation performance of an NMOSFET current mirror with a capacitor connected between the mirror node and the ground. Closed-form approximate expressions are obtained for the dc and the amplitudes of the fundamental, second- and third-harmonic, and second- and third-order intermodulation output current components resulting from exciting the mirror by a dc biasing current plus a superimposed multisinusoidal EMI. Simulation results are included. [ABSTRACT FROM PUBLISHER]

This paper has developed two techniques to reduce the parasitic parameters and improve the high-frequency performance of the planar integrated electromagnetic interference (EMI) filter. First, each developed technique has been analyzed, respectively, then the performance of an EMI filter with both the developed techniques has been researched. The research contents are as follows. 1) Analyzing the improvement of the equivalent parallel capacitance (EPC) for a common mode (CM) EMI filter by two CM windings overlapped and interleaved layout. The EPC of the integrated EMI filter is about 14% of the reference EMI filter. 2) Analyzing the improvement of the equivalent series inductance (ESL) in the parallel branch for a CM EMI filter by each CM winding coupled with two ground winding layers. The resonance frequency brought by ESL is shifted to a higher frequency. At 30 MHz, the insertion loss is increased by 45 dB compared with the reference. In the mean time, the structure is equivalent to a two-stage L-type low-pass filter, which can largely increase the high-frequency attenuation compared with the one-stage L-type low-pass filter for the reference one. (3) Researching the performance of an EMI filter with both the proposed techniques. The developed EMI filter can not only decrease the EPC, but also reduce the negative effect of ESL. The developed EMI filter improves the high-frequency performance dramatically compared with the EMI filter with only one of the developed techniques. In the mean time, the differential mode (DM) capacitor is formed by the two overlapped and interleaved windings, and does not need an extra lumped DM capacitor. Therefore, CM inductors, CM capacitors, and DM capacitors can be integrated in the overlapped and interleaved L–C winding structure, so miniaturized EMI filter can be realized. The experiment results indicate effectiveness of the developed integrated EMI filters, and the cost and complexity is the same as the reference EMI filter. [ABSTRACT FROM PUBLISHER]

Ringing in the switching waveform of the switching power supply (e.g., synchronous buck converter) is known to cause broadband electromagnetic interference problems in the 30–300 MHz range. The measured switching waveform shows overshoot and, then, exponential decay of the ringing. It has been observed that this exponential decay rate varies significantly between using different low-side FETs; thus, the low-side FET dominates the attenuation of the ringing. This paper provides a novel method for quantifying the losses by using the measureable quantity “ Ross,” which is equivalent to the loss of the output capacitance C oss of the FET. This paper describes the method of measuring Ross and explains its relevance to the self-damping of the switch ringing. The method permits selection of a low-side FET to optimize the electromagnetic compatibility performances of the supply. [ABSTRACT FROM AUTHOR]

In this paper, fast capacitor assignment algorithms capable of finding a decoupling solution scheme with a minimum number of components that meets a predefined target impedance with a semi-arbitrary shape within a few seconds to an hour for a given power distribution network (PDN) are proposed. The proposed algorithms also provide identification of shadowed decap ports in a PDN based on an inductance matrix extraction from the given PDN model. Elimination of those shadowed decap ports with the proposed algorithms enables more effective layouts and cost savings on PCB designs. [ABSTRACT FROM PUBLISHER]

This paper presents a novel fully integrated step-up dc/dc converter containing circuits to improve electromagnetic emissions. This design utilizes current sources to limit the impulsive current flow into the integrated flying capacitors. This reduces the discontinuous pulse currents normally associated with capacitive converters causing electromagnetic interference (EMI). A variable reference current enables the converter to operate with the lowest possible emissions through the entire operating range and is used to regulate the output voltage. The inclusion of low EMI techniques enables fully integrated power converters to be implemented in systems where noise produced by converters currently restricts or prohibits their use. The proposed 3.2 mW voltage doubler was fabricated in a 0.18 $\mu$m CMOS process. With an input voltage range of 1–1.8 V, the converter produces a 1.6–3.3 V output. Experimental results verify the reduction of emissions to meet IEC 61967-4 Class L using current control with a reduction of noise voltage when compared with the circuit without the proposed techniques. [ABSTRACT FROM AUTHOR]

This paper presents a novel non-uniform time-step (NUTS) fundamental locally one-dimensional (FLOD) finite-difference time-domain (FDTD) method for multiconductor transmission lines (MTLs) including lumped elements. The NUTS scheme adopts different (non-uniform) time steps for different periods during simulation, in order to reduce the large errors caused by unconditionally stable FDTD methods with uniform time step larger than Courant-Friedrichs-Lewy limit. It is found that NUTS scheme is potentially unstable for alternating-direction-implicit (ADI) FDTD method, but it is stable for LOD-FDTD method or its implementation based on fundamental (FLOD) scheme. The NUTS FLOD-FDTD method is useful to simulate MTLs with lumped elements including resistor, capacitor, and inductor in series and parallel connections. Moreover, the method based on multiple 1-D approach is also extended to incorporate lumped elements in cross connection to model near-field coupling between the MTLs. While the electric current density is commonly used for field-circuit coupling of parallel connected lumped elements, the magnetic current density will be utilized for field-circuit coupling of series and cross-connected lumped elements. Numerical results for MTLs with lumped elements in series, parallel, and cross connections are provided to show the trade-off between efficiency and accuracy of the proposed NUTS FLOD-FDTD method. Compared with the FLOD-FDTD method with uniform time step, the NUTS FLOD-FDTD method may achieve higher accuracy by using smaller time step for certain periods of simulation. [ABSTRACT FROM PUBLISHER]

In this paper, the effects of parasitic couplings in electromagnetic interference (EMI) filters are investigated using an equivalent circuit analysis and experiments. The investigated filter has the C-L-C filter structure which is composed of foil capacitors, feedthrough capacitors, and a toroidal inductor. The parasitic couplings between input capacitors and output capacitors increase the transfer function of the filter. We found that the increase of the transfer function is caused by two kinds of parasitic couplings: one is the parasitic inductive coupling between the two resonance circuits which are composed of feedthrough capacitors and foil capacitors, and another is the parasitic capacitive coupling between the input and the output foil capacitors. Balancing the two parasitic couplings, it is possible to reduce the transfer function increase without increasing the filter size. The experimental results of transfer functions agree with the equivalent circuit analysis results up to 30 MHz. The balancing condition obtained by the circuit analysis has been confirmed by the experiments. [ABSTRACT FROM AUTHOR]

This paper presents an electromagnetic interference (EMI) evaluation method for ICs in mobile devices. The evaluation method consists of a noise measurement method for ICs and a qualification specification, which has a direct correlation with system-level radiated emissions. The 1-\Omega direct coupling method, which belongs to the IEC 61967 standard, is adopted to measure the conducted emission from a specially designed low-voltage differential signaling loop-back test IC. To devise the specification for the IC-level EMI evaluation, a definite correlation between the conducted emission from the IC and the radiated emission from a test system, which consists of a printed circuit board with the IC and an attached power cable, was obtained as a radiation transfer function (RTF). By combining the RTF with the system-level regulation specification provided by CISPR or FCC, an EMI evaluation specification for the test IC was derived. For several test cases, we measured the conducted emissions from the IC to assess the noise level and pass/fail statement. Compared with the radiated emissions from the test system, it was observed that there is a meaningful correlation in terms of the emission peak level and the pass/fail decision. The proposed methodology can be applied to component-level EMI assessment at the early design stage of modern high-speed mobile devices and will be very helpful in reducing system-level EMI problems and design failures in advance. [ABSTRACT FROM PUBLISHER]

This paper proposes a simple method to enhance the timing margin of high-speed digital signals for multiconductor transmission lines (MTLs) in inhomogeneous media. It uses interline capacitances to implement the capacitance matrix homogenizing the original inhomogeneous structure. As a result, it equalizes the velocities of all the modes involved in the MTL structure simultaneously. The design equations are derived and the limitation of the proposed scheme is explained. For the experiment, a 100-mm three-line coupled microstrip MTL (M-MTL) is built. The measured total peak-to-peak jitter including crosstalk and other noises was 91 ps in the test structure. When the M-MTL is loaded by the proposed values of lumped capacitors between the adjacent lines, the jitter is reduced to 12 ps, whereas the measurement using the even/odd mode approach shows 22 ps jitter. All the measurement results are in good agreement with the theoretical values, which proves the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper analyzes the transformation between differential-mode and common-mode noises due to the unbalance of noise sources and electromagnetic interference filters in power electronics circuits. Both insertion gain and electromagnetic interference measurements prove the analysis. [ABSTRACT FROM AUTHOR]

Capacitors with two or three leads tend to make poor low-pass filters at high frequencies (e.g., > 100 MHz) due to the mutual inductance between the input and output sides of the filter. This paper proposes a four-lead low-pass filter capacitor design that minimizes the magnetic flux coupling between the input and output. Measurements of a prototype capacitor confirm that it performs significantly better than a typical two-lead capacitor at high frequencies. [ABSTRACT FROM AUTHOR]

Demand and interest in wireless power transfer (WPT) have been rapidly increasing lately. However, WPT systems have problems with electromagnetic field (EMF) leakage, which has stimulated interest in methods to suppress EMF leakage levels. In this paper, we propose a compact resonant reactive shielding coil topology for reducing EMF in a near-field WPT mobile device application. The proposed shielding coil employs a closed loop and matching capacitors, and is demonstrated to dramatically reduce the leakage magnetic field from a WPT system. For validation, the proposed shielding was implemented with other shielding topologies and the EMFs were measured and compared. The analytical, simulation, and measurement results were all strongly correlated. [ABSTRACT FROM PUBLISHER]

Disturbances in low-voltage control circuits in substations and power plants occur due to lightning or switching surges. Adequate protection of electronic devices in low-voltage control circuits requires the capacity to predict surge phenomena and to evaluate the effectiveness of protection methodologies. In this paper, we present and validate a technique to represent twisted-wire pairs, which are commonly used in control circuits, for surge simulations using the Finite-difference time-domain method combined with the Agrawal et al. model. [ABSTRACT FROM PUBLISHER]

The evaluation of electromagnetic parasitics is important for electromagnetic interference within power electronics systems. Simple yet accurate physics-based lumped-circuit models of these parasitics can facilitate fast analysis and better understanding of the system performance. Methods exist to reduce complex electromagnetic models to much simpler representations but, while they speed up calculation, they do not preserve physicality. In this paper, a methodology is developed for obtaining a simplified SPICE circuit from a large-scale partial element equivalent circuit (PEEC) model, where there is a clear correlation between geometry and parasitic circuit elements. To preserve correlation between equivalent circuits and physical geometry, reduction is done first for inductance and resistance; then, reduction is performed for capacitance using nodes from the reduced LR model. The reduced model gives a better insight into the causes of and possible solutions to electromagnetic problems and can be used to improve the design. The method was validated on real power electronics geometries using frequency-dependent behavior of port impedances and admittances. The initial PEEC model for this example contained approximately 10 645 unknowns and was reduced to 195 elements. The calculated and measured impedances agree within 0.1 dB up to 200 MHz. [ABSTRACT FROM PUBLISHER]

Although the dc/dc converter as a common power supply is compatible with the electromagnetic compatibility standard, it may still bring the peak interference generated from one nonlinear load to the other loads. In this paper, a novel filter is designed in a low-voltage buck converter to suppress some extra peak harmonics generated from a nonlinear load, i.e., a pulse width modulation switching circuit. This filter is a variable capacitance filter (VCF) whose active devices are working in the linear areas. The capacitance of the filter is controlled to vary with the change of the switching load's carrier-frequency in the scheme. The impedance of the VCF can not only be matched with the switching load, but also avoid the mismatch effect from the parameter drift caused by the aging of the components. Thus, the VCF can suppress the introductive peak harmonics from the switching load at its carrier-frequency, especially the peak harmonics in the carrier-frequency region when the carrier-frequency modulation is used as the control strategy in the switching load. The feasibility and validity of the VCF are proved by simulations and experiments in a low-voltage buck converter, in which a boost circuit is working as one of its loads. [ABSTRACT FROM AUTHOR]

In this paper, a coupled miscrostrip line using the front-end decoupling capacitor is proposed to suppress the far-end crosstalk noise of the coupled microstrip line. The far-end crosstalk noise is greatly reduced from 63 to 25.7 mV. In order to further reduce the far-end crosstalk noise, a coupled microstrip line using the distributed decoupling capacitors is proposed. As compared with the coupled microstrip line using the front-end decoupling capacitor, the far-end crosstalk noise is further reduced from 25.7 mV to nearly 0 mV. In order to verify the simulation results, two coupled microstrip line circuits are fabricated and measured where the measurement results are in good agreement with the simulation results. [ABSTRACT FROM AUTHOR]

In this paper, we propose and study several new designs of a shunt capacitor filter with two surface-mount technology capacitors. These designs make use of mutual inductance effects to increase the attenuation provided by the filter in the range of high frequencies where the filter behaves inductively. We provide lumped element circuit models for the proposed designs that allow identification of the key inductive parameters that determine the high-frequency performance of these filters. We obtain the equations relating these parameters to the effective inductance of the filter, which can be used to compare the high-frequency behavior of different filter designs. We have fabricated and measured several compact shunt capacitor filters with improved performance at high frequencies. We have found that, compared with a shunt capacitor filter with one capacitor, a proper filter design with two capacitors can easily increase in 15–20 dB the high-frequency attenuation provided by the filter. This design also outperforms by 10–15 dB a traditional shunt capacitor filter with two capacitors closely placed. Moreover, this improvement is obtained with no increase in size, cost, or time of design of the filter. [ABSTRACT FROM AUTHOR]

This paper presents a methodology dedicated to modeling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz. [ABSTRACT FROM AUTHOR]

Switching current drawn by an integrated circuit (IC) creates dynamic power supply noise on the IC and on the printed circuit board (PCB), which in turn causes jitter in I/O signals and reduces the maximum clock frequency. Predicting power supply noise is challenging due to the complexity of determining the dynamic current drawn by the IC and the impedance of the power delivery network. In this paper, a methodology is developed for predicting dynamic power supply noise on the PCB resulting from logic activity in a field-programmable gate array (FPGA). Time-domain switching currents within the FPGA are found by performing power simulations of the implemented logic over small time intervals. A high-frequency model of the die–package–PCB power delivery network is developed based on the inductance and capacitance of the package and die and a cavity model description of the PCB. The technique is shown to accurately predict noise on the PCB in both the time and frequency domains. [ABSTRACT FROM AUTHOR]

In this paper, a complete new methodology for the automated design of power-line filters is presented and tested. It is based on rigorous characterizations of power-line-filter components, devices under test, and line-impedance stabilization networks (or power-line networks) by means of S-parameter and interference measurements. The implemented automated design tool is able to find an optimal power-line filter for a given device under test under constraints such as cost or number of components, drastically reducing the design time as compared to the usual trial-and-error practice. Since the features of common-mode chokes are highly dependent on the 50-Hz current levels flowing through them, a measurement system of common-mode chokes under 50-Hz load conditions has also been developed and tested in order to complement the automated design tool. The whole system has been successfully validated by means of experimental measurements. [ABSTRACT FROM PUBLISHER]

The traveling-wave Marx generator was first proposed by Carl Baum to analyze the switch-closure propagation process in fast pulsed-power systems. To improve the performance of the transistorized sub-nanosecond pulse generator, the traveling-wave Marx circuit with inter-stage transmission lines is studied. Simulations indicate that the delay time and the impedance of inter-stage transmission lines [microstrip lines on printed circuit board (PCB)] are main factors affecting the pulse waveform. Based on it, the series connection of modularized Marx circuits is proposed, which has the advantages of adjustable amplitude and bendable circuit layout. A compact high-amplitude pulse generator is developed with the amplitude of 8.2 kV, the rise time of 150 ps, and the PCB length of 35 cm. For higher pulse repetition rate, the heat dissipation design of PCB is necessary; however, due to the variations in the microstrip line structure, the commonly used metallic heat sink may cause a significant decrease in pulse amplitude. Thus, a novel heat dissipation design is proposed by optimizing the layout of metallic sinks and introducing heat-conducting ceramic sinks. A high-repetition-rate pulse generator is developed with the maximum pulse repetition rate of 600 kHz, the amplitude of 1.1 kV, and the rise time of 160 ps. [ABSTRACT FROM AUTHOR]

This work analyzes the effect of conducting bands placed close to a common mode choke on the attenuation provided by an electromagnetic interference filter where the common mode choke is mounted. The main aim was to determine whether the response of the common mode choke can be modified and to clearly identify and quantify the physical mechanism responsible for the changes found in the attenuation of the common mode choke and the electromagnetic interference filter. The impact of grounded and ungrounded conducting surfaces was studied for the two more typical configurations of common mode chokes: vertically and horizontally mounted. This study has allowed us to devise an optimum shield for a common mode choke that can significantly improve the attenuation to both common mode and differential mode noise of an electromagnetic interference filter at high frequencies, where parasitic effects usually undermine the performance of the filter. Key features of the technique described here are that it can be applied easily and that it does not result in an increase of the weight, volume, or cost of the filter. [ABSTRACT FROM AUTHOR]

This paper describes an industry-oriented approach for the analysis of complex electronic systems. The typical constrains of an industry design flow such as limited time, limited computing resources, and the use of standard/commercial software tools are considered. The approach consists in partitioning the system in several functional blocks and studying each block separately. Different numerical techniques are employed, choosing the more appropriate, for characterizing each chain blocks. At the end, all the blocks are cascaded obtaining the overall system performances. The approach is applied to a voltage supply chain mounted on board of the SENTINEL 1-SAR satellite to verify the integrity of the voltage pulse propagating from the source to the high power amplifiers. The final results are validated by hardware measurements. [ABSTRACT FROM AUTHOR]

Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed. [ABSTRACT FROM AUTHOR]

As is known, undesired simultaneous switching noise produced by high-speed digital integrated circuits (ICs) and power vias may propagate along parallel-plane structures of multilayer printed circuit boards (PCBs) and IC packages, which act as parallel-plane cavity resonators.To minimize effects of the parallelplane cavities, we need to minimize the impedance profile of a PCB power bus in the frequency range of interest.We can minimize the impedance profile by reducing power bus plane spacings, and by using local and global decoupling techniques that employ decoupling capacitors. But, in the gigahertz-range, discrete capacitors are not efficient due to the parasitic inductance of their connections to the power bus. In this paper, in addition to the analysis of cavity-mode resonances in multilayered PCBs, we derived expressions for the impedance envelope that can be used for predicting the impedance profile of a power bus. This theoretical approach and the derived envelope expressions are confirmed analytically by the cavity-model method, by a full-wave field solver, and by laboratory measurements carried out by a network analyzer. [ABSTRACT FROM AUTHOR]