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Resistive switching memory (RRAM) is among the most mature technologies for next generation storage class memory with low power, high density, and improved performance. The biggest challenge toward industrialization of RRAM is the large variability and noise issues, causing distribution broadening which affects retention even at room temperature. Noise and variability can be addressed by enlarging the resistance window between low-resistance state and high-resistance state, which requires a proper engineering of device materials and electrodes. This paper presents an RRAM device technology based on silicon oxide (SiOx), showing high resistance window thanks to the high bandgap in the silicon oxide. Endurance, retention, and variability show excellent performance, thus supporting SiOx as a strong active material for developing future generation RRAMs. [ABSTRACT FROM AUTHOR]

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiOx) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the 10~\mu \texts –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays. [ABSTRACT FROM PUBLISHER]

The high current density required by magnetic tunneling junction (MTJ) switching driven by the spin transfer torque (STT) effect leads to large power consumption and severe reliability issues, hindering the timetable for STT magnetic random access memory to mass market. By utilizing the voltage-controlled magnetic anisotropy (VCMA) effect, the MTJ can be switched by the voltage effect and is postulated to achieve ultralow power (fJ). However, the VCMA coefficient measured in experiments cannot meet the requirement for MTJ with dimensions below 100 nm. And an external in-plane magnetic field usually is demanded for precessional VCMA switching. Here, in this paper, a novel approach for the amplification of the VCMA effect, which borrows ideas from negative capacitance, is proposed. The feasibility of the proposal is proved by physical simulation and in-depth analysis. Since the amplified VCMA effect, the external magnetic field can be eliminated. A three-terminal novel MTJ memory cell is designed with which both low power and high speed can be achieved. [ABSTRACT FROM AUTHOR]

A key concern for resistive-switching random access memory (RRAM) is the read noise, due to the structural, chemical, and electrical modifications taking place at the localized current path, or conductive filament (CF). Read noise typically appears as a random telegraph noise (RTN), where the current randomly fluctuates between ON and OFF levels. This paper addresses RTN in RRAM, providing physical interpretations and models for the dependence on the programming and read conditions. First, we explain the RTN dependence on the compliance current during set transition in terms of the size-dependent depletion of carriers within the CF. Then, we discuss the bias dependence of the RTN switching times and amplitude, which can be explained by Joule heating and Poole-Frenkel barrier modifications arising from the electrostatics of the RTN fluctuating center. [ABSTRACT FROM AUTHOR]

A highly transparent resistive random access memory with a configuration of multilayer graphene (MLG)/ Dy2O3 /indium tin oxide (ITO) structure is demonstrated in this paper. The fabricated device is transparent, with 80% transmittance at 550 nm. The MLG/ Dy2O3 /ITO device shows unipolar resistance switching with a low operation current (<100~\muA) , low operation voltage (<1~V) , low power consumption (<100~\muW) , high resistance ratio (>10^4) , fast switching speed (<60~ns) , reliable data retention, and promising cycle endurance properties (>200~cycles) , which makes a step toward the realization of low-power transparent electronics for next-generation nonvolatile memory application. The MLG/ Dy2O3 /ITO device exhibited typical filamentary-conduction-type resistive random access memory behavior and no forming process is required. High resistance state (HRS) increases with a reduced device area while low resistance state (LRS) is insensitive to the device sizes. Moreover, Raman spectra obtained in pristine state, HRS, and LRS indicate that the lower power consumption of MLG/ Dy2O3 /ITO device is attributable to the formation of oxygen graphene layers. [ABSTRACT FROM AUTHOR]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

Metal/NiO/Pt films with various electrodes were fabricated to investigate the effects of standard free energy (SFE) on NiO resistive switching devices. By selecting Ti, Ta, Ag, Cu, and Co as the top electrodes (TEs), we found that the switching voltage was inversely proportional to the SFE. The reason for this is attributed to the different thicknesses of the oxidized interface between TE and NiO. Since the thickness of the oxidized interface depends on the SFE, this paper provides an effective way to control and adjust the switching voltage. [ABSTRACT FROM PUBLISHER]

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

This paper investigates and models the dc behavior of thin-film-based switching devices. The devices are based on sputtered vanadium dioxide thin films that transition from 200 k\Omega/\square at room temperature to 390 \Omega/\square at temperatures above 68^\circC, with the transition occurring over a narrow temperature range. The device resistance is characterized over temperature and under current- and voltage-sourced electrical bias. The finite-element model predicts the device's nonuniform switching behavior. Electrothermally heated devices show the same transition ratio and switching behavior as externally heated devices suggesting a purely electrothermal switching mechanism. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level. [ABSTRACT FROM PUBLISHER]

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a $4 \times 4$ crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology. [ABSTRACT FROM PUBLISHER]

The efficiency of the human brain in performing classification tasks has attracted considerable research interest in brain-inspired neuromorphic computing. The spiking neuromorphic architectures attempt to mimic the computations performed in the brain through a dense interconnection of the neurons and synaptic weights. A leaky-integrate-fire (LIF) spiking model is widely used to emulate the dynamics of the biological neurons. In this paper, we propose a spin-based LIF spiking neuron using the magnetoelectric (ME) switching of ferromagnets. The voltage across the ME oxide exhibits a typical leaky-integrate behavior, which in turn switches an underlying ferromagnet. Due to the effect of thermal noise, the ferromagnet exhibits probabilistic switching dynamics, which is reminiscent of the stochasticity exhibited by biological neurons. The energy efficiency of the ME switching mechanism coupled with the intrinsic nonvolatility of ferromagnets results in lower energy consumption, when compared with a CMOS LIF neuron. A device to system-level simulation framework has been developed to investigate the feasibility of the proposed LIF neuron for a hand-written digit recognition application. [ABSTRACT FROM AUTHOR]

This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker–Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a test system for active-matrix organic light emitting diode (AMOLED) panels with various pixel structures with the external compensation method. The proposed AMOLED panel test system employs universal data drive ICs to measure the current of a driving thin-film transistor (TFT) and the anode voltage of the OLED in various pixels by only programming the field-programmable gate array in the proposed test system. The universal data driver IC are fabricated and implemented in the proposed AMOLED panel test system whose test board is assembled with a 55-in full-high-definition AMOLED panel. A fabricated universal data driver IC includes 640 data channels with a 12-b linear gamma digital-to-analog converter and 12-bit variable current sources. To evaluate the repeatability error of the proposed panel test system, the current of the driving TFT is repeatedly measured and the measured maximum repeatability error is 9.8 nA. In addition, to evaluate the measurement accuracy of the proposed panel test system, the variation in the currents of the driving TFTs is measured and compensated for, and its maximum value after compensation is 26 nA. [ABSTRACT FROM PUBLISHER]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

The effect of voltage on the anisotropy of a magnetic tunnel junction (MTJ) is of substantial interest for low-power nonvolatile memory applications. In this paper, we develop a device-to-bit-cell level simulation framework for voltage-assisted switching of the MTJs, which can satisfactorily reproduce the published experimental data. Our simulation framework is based on a coupled Landau–Lifshitz–Gilbert–Slonczewski equation and nonequilibrium greens function formalism. Using this simulation framework, we investigate the effect of scaling the oxide thickness of an MTJ to enhance the electric field effect. Although it seems attractive for an isolated device, yet, in a bit-cell configuration, reducing the oxide thickness leads to an increase in the supply voltage. In addition, we demonstrate that the unipolar characteristic of the voltage-assisted switching leads to write failures depending on the initial state stored in the MTJ. We, therefore, suggest a read before write scheme exhibiting approximately $2\times $ improvement in the write energy consumption at a bit-cell level compared with a standard STT-MRAM for iso-oxide thickness. However, the latency overhead associated with voltage-assisted MTJs results in a $1.55\times $ degradation of the write speed. Moreover, our layout analysis indicates that the bit-cell area reduction is constrained by the metal pitch, in spite of smaller access transistors. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the \FOMT. [ABSTRACT FROM PUBLISHER]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

This paper reports on the first demonstration of a reconfigurable complementary-metal–oxide–semiconductor (CMOS) oscillator based on microelectromechanical system (MEMS) resonators operating at four different frequencies (268, 483, 690, and 785 MHz). A bank of multifrequency switchable AlN contour-mode MEMS resonators was connected to a single CMOS oscillator circuit that can be configured to selectively operate in four different states with distinct oscillation frequencies. The phase noise (PN) of the reconfigurable oscillator was measured for each of the four different frequencies of operation, showing values between -94 and -70 dBc/Hz at a 1-kHz offset and PN floor values as low as -165 dBc/Hz at a 1-MHz offset. Jitter values as low as a 114-fs root mean square (integrated 12 kHz–20 MHz) and switching times as fast as 20 \mu\s were measured. This first prototype represents a miniaturized solution (30 times smaller) over commercially available voltage-controlled surface-acoustic-wave oscillators and potentially has the advantage of generating multiple stable frequencies without the need of cumbersome and power-consuming phase-locked-loop circuits. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic random-access memory (STT-MRAM) based on a single-barrier magnetic tunnel junction (SBMTJ) and a double-barrier magnetic tunnel junction (DBMTJ) has evolved along with a low switching current and low energy consumption to obtain a high areal density and a fast switching speed. The increment of initial temperature, ${T}_{{\text {in}}}$ , in STT-MRAM can achieve low switching energy, ${E}_{{\text {SW}}}$. However, this leads to an unavoidable decrease in $\Delta $ and switching efficiency. In this paper, SBMTJ and DBMTJ were analyzed in terms of the switching efficiency factor with ${E}_{{\text {SW}}}$ reduction by increasing the ${T}_{{\text {in}}}$. The switching temperature, ${T}_{{\text {SW}}}$ , was investigated using a finite-element method simulation. The results show that the DBMTJ(A) and SBMTJ with the same MgO layer thickness of 0.9 nm provide a higher switching current, ${I}_{{\text {C}}}$ , than the DBMTJ(B) with a MgO layer thickness of 1.3 nm. The ${T}_{{\text {SW}}}$ in a DBMTJ(A) is higher than that in an SBMTJ, while ${T}_{{\text {SW}}}$ for a DBMTJ(B) is the smallest because of its low ${I}_{{\text {C}}}$. The DBMTJ(A) and DBMTJ(B) can be applied in a higher temperature range than the SBMTJ at a $\Delta $ of 40. In addition, the STT efficiency factor, $\Delta /{I}_{{\text {C0}}}$ , for a DBMTJ is better than the factor for an SBMTJ. Although the temperature increment would cause an undesirable reduction in $\Delta $ , it can reach a low ${E}_{{\text {SW}}}$ for the requirement of a fast write access time. Therefore, the control device for increasing the ${T}_{{\text {in}}}$ in the MTJs is attractive and should be promoted in the advancement of memory technology. [ABSTRACT FROM AUTHOR]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits. [ABSTRACT FROM AUTHOR]

The degradation behavior of Ag/SiO2-based conductive bridging RAM (CBRAM) is analyzed by conventional and expanded time-dependent dielectric breakdown (TDDB) models. By comparing the total cycling stress with time-to-breakdown (${t}_{\text {bd}}$) of the SiO2 used as a solid-electrolyte switching layer, it is clarified that the cycling stress does not reach the level at which dielectric breakdown of the SiO2 is triggered. On the other hand, we found that the ${t}_{\text {bd}}$ distribution after several cycles of set/reset stress agrees well with the simulated ${t}_{\text {bd}}$ distribution derived from expanded TDDB models, in which we assumed that a large amount of defects exists locally in the device area. This approach is useful for understanding the degradation in solid-electrolyte oxide of CBRAM. [ABSTRACT FROM AUTHOR]

A novel ultrafast and low-loss lateral injection-enhanced gate transistor (LIEGT) is proposed and investigated by simulation. The device features a MOS-controlled shorted anode (MCSA) and a bias voltage (${V}_{{AG}}$) applied between the anode trench gate (ATG) and the anode electrode. The n+ anode is shorted to the N-buffer through the MOS channel around the ATG when the MCSA is activated with ${V}_{{AG}} > {V}_{{th}}$ during turn-off and blocking states, and thus the p+ anode/N-buffer junction is unactivated. The MCSA LIEGT turns off as fast as a unipolar device by optimizing the time gap to activate the MCSA before turning off the cathode trench gate (CTG). The activated MCSA would deactivate hole injection from the anode side and synchronously quickly extract the electrons from the N-drift, which improves the switching speed and dramatically decreases the turn-off energy loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$). In the blocking state, the MCSA LIEGT achieves a MOS breakdown mode instead of an open base p-n-p bipolar breakdown mode. Thus, the breakdown voltage (BV) is not only improved but also independent of the p+ anode doping concentration. In the forward conduction state with ${V}_{{AG}} = {0}$ , the MCSA is unactivated and hence the MCSA LIEGT operates like a conventional LIEGT without deteriorating the on-state voltage drop (${V}_{ \mathrm{\scriptscriptstyle ON}}$). Compared with the conventional LIEGT, the proposed device decreases ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 88% and improves the BV by 13% at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$. Importantly, ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is almost independent of ${V}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density. [ABSTRACT FROM AUTHOR]

We demonstrate the ink-jet printed fabrication technique for TiO2-based memristor, followed by detailed analysis of electrical characteristics and development of a new model that considers observed phenomena of quantized conductance steps. The existence of pinched hysteretic current–voltage characteristics is evidence of memristive behavior, provided by the reversible atomic rearrangement taking place in the functional layer. For the first time, performed electrical measurement on the micrometer thickness devices based on TiO2 active layer has captured the plateaux steps of the conductance at integer multiples of elementary quantum conductance. This behavior is consistent with the assumption that transport from electrode to electrode emerges through confined paths of conductive filaments with radius in the nanometer size range. Moreover, we introduce a novel model, based on the diffusion equation for ballistic transport in memristive devices, which considers the conductance plateaux steps. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]

This paper proposes a domain-wall-coupling-based magnetic device for high-speed and robust on-chip cache applications. The read and write current paths are magnetically coupled and electrically isolated, which significantly improves the reliability of the read and write operations. Our proposed device makes use of fast and energy-efficient domain wall motion for write operation. A complementary polarizer structure is used to achieve low-power, high-speed, and high-sensing margin read operations. A device-to-circuits simulation framework was also developed to evaluate our proposed multiterminal domain-wall-coupling-based spin-transfer torque (DWCSTT) magnetic random access memory (MRAM) cell. Compared with the conventional 1T-1MTJ STT-MRAM bit cell, the proposed DWCSTT bit cell achieves >3.5\times improvement in write power under iso-area and iso-write margin conditions, and $>\!\!3\times $ better sensing margin with low read power consumption and higher read disturb margin. [ABSTRACT FROM AUTHOR]

Owing to their nonvolatility, outstanding endurance, high write and read speeds, and CMOS process compatibility, spin-transfer torque magnetoresistive memories (MRAMs) are prime candidates for innovative memory applications. However, the switching delay of their core components—the magnetic tunnel junctions (MTJs)—is a stochastic quantity. To account for this in electronic design, only partial models (working in extreme regimes) are available. In this paper, we propose an analytical model for the stochastic switching delay of a current-driven MTJ, with in-plane magnetization, that agrees with physical simulations, from low- to high-current regimes through intermediate regime. We performed physical macrospin simulations of MTJs for a wide range of current. We developed an analytical model for the mean switching delay that fits those simulations results, and smoothly connects well-accepted models for the extreme low and extreme high currents limits. In addition, a probability distribution in agreement with our simulations results is proposed, leading to a full model of the stochastic switching delay. An example for the application of the model is proposed. Our analytical model can help to evaluate the error rate in MRAM designs, and allow designing innovative electronic circuits that exploit the intrinsic stochastic behavior of MTJs as a beneficial feature. [ABSTRACT FROM PUBLISHER]

An intentionally introduced interface layer in the resistive random-access memory (RRAM) devices play an important role in the improvement of resistive switching characteristics. In this paper, the resistive switching characteristics of ZrO2-based RRAM devices by inserting a thin TiO2 interface layer between electrodes and ZrO2 resistive switching layer were investigated. Compared with the Cu/ZrO2/Pt and Cu/ZrO2/TiO2/Pt devices, the Cu/TiO2/ZrO2/Pt and Cu/TiO2/ZrO2/TiO2/Pt devices showed much improved programing voltages, including lower forming voltage and lower set voltage. Moreover, the reset current was also improved. These results indicate that the TiO2 interface layer between the anode electrode and the resistive switching layer plays an important role in improving device performance. [ABSTRACT FROM AUTHOR]

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 109 cycles is achieved, and read endurance is higher than 1011 cycles. [ABSTRACT FROM AUTHOR]

The subthreshold behavior of floating-gate MOSFETs connected with ferroelectric capacitors (FeCs) was investigated experimentally and theoretically. We found that the subthreshold swing (SS) decreases with decreasing ferroelectric capacitance (i.e., with the decreasing FeC area), in contrast to the voltage dividing effect of regular dielectric capacitors. The ferroelectric polarization switching counteracts the effect of voltage dividing by introducing an additional charge onto the floating gate, which improves the SS and leads to the observed SS dependence. The SS improvement caused by the polarization switching is different from the negative capacitance effect, which is helpful to further understand the ferroelectric transistor. [ABSTRACT FROM AUTHOR]

Reducing the energy and power dissipation of conductive bridge random access memory (CBRAM) cells is of critical importance for their applications in future Internet of Things (IoT) device and neuromorphic computing platforms. Atomically thin CBRAMs enabled by 2-D materials are studied theoretically by using 3-D kinetic Monte Carlo simulations together with experimental characterization. The results indicate the performance potential of attoJoule energy dissipation for intrinsic filament formation and a filament size of a single atomistic chain in such a CBRAM cell. The atomically thin CBRAM cells also show qualitatively different features from conventional CBRAM cells, including complete rupture of the filament in the reset stage and comparable forming and set voltages. The scaling and variability of the CBRAM cells down to sub-nanometer size of the switching layer as realized in the experiment are systematically studied, which indicates performance improvement and increased relative variability as the switching layer scales down. The results establish the ultimate limits of the size and energy scaling for CBRAM cells and illustrate the unique application of 2-D materials in ultralow power memory devices. [ABSTRACT FROM AUTHOR]

Electrical control of magnetic tunnel junctions (MTJs) provides opportunities to introduce MTJs into high-performance applications requiring low power consumption. The magnetic state of an MTJ can be electrically controlled through: 1) the spin transfer torque (STT) effect; 2) the voltage controlled magnetic anisotropy (VCMA) effect; and 3) the fusion of STT and VCMA. Several compact models have been published for MTJs. All of these models consider an MTJ whose magnetic state is controlled through the STT effect. In this paper, a model of an MTJ comprising a free layer, an analysis layer, and a spin polarizing layer is described. The MTJ compact model, adaptive compact MTJ (ACM) model, includes the effects of asymmetry on the MTJ behavior, and models a device controlled through the STT, VCMA, or a fused STT–VCMA mechanism. The ACM model includes the dynamics of the junction temperature. The proposed model can be adapted to experimental configurations including in-plane MTJ (IMTJ), IMTJ with a perpendicular-to-the-plane polarizer, perpendicular-to-the-plane MTJ (PMTJ), and PMTJ with an additional easy axis. The ACM model is validated with published experimental data, showing reasonably accurate results with an average error of less than 6%. [ABSTRACT FROM AUTHOR]

The recently discovered ferroelectric behavior of HfO2-based dielectrics yields the potential to overcome the main challenges of the ferroelectric field-effect transistors (FeFETs)—CMOS compatibility as well as scalability to the state-of-the-art technology nodes of logic transistors. In this paper, we study the impact of scaling on the memory performance of FeFET devices employing Si:HfO2 ferroelectric films. The operation capability was proven down to a gate length of 28 nm. Program/erase characteristics, endurance behavior, and retention properties were analyzed for FeFETs with gate lengths scaled down to 32 nm. The detected difference in the performance between the long and short channel devices could be for the most part attributed to transistor short channel effects. In addition, the effect of temperature on the device properties of Si:HfO2-based FeFETs was investigated in detail. The program/erase speed was ascertained to be independent of temperature. On the other hand, increase in temperature resulted in reduced initial memory window accompanied by its slightly accelerated decay with time. [ABSTRACT FROM AUTHOR]

An ideal switch with hysteresis-free \(S_{\rm ideal}=0~{\rm mV/decade}\) switching is desired to keep Moore’s law alive, but has never been achieved. Classical field-effect transistors (FETs) have supported Moore’s law for 50 years, albeit with a thermodynamically limited value of subthreshold swing \(S\ge 60\) mV/decade. Alternatives, such as, tunnel FETs, impact ionization FETs, and negative capacitance FETs promise \(S <60\) mV/decade, but ideal switching is not expected, even in theory. In this paper, we propose a zero subthreshold swing FET (ZSubFET), which is similar to a classical FET with a suspended-gate and a ferroelectric gate insulator. ZSubFET exhibits ideal switching through integration of two negative capacitors (namely, a ferroelectric and an air-gap) in the gate-stack, in series with the channel capacitance. We believe that the proposed device concept should not only lower the power dissipation in an IC, but also open up new research directions for the alternative of classical-FET. [ABSTRACT FROM AUTHOR]

This paper reports the design, fabrication, characterization, and scaling analysis of novel buckling-based nanoelectromechanical relays that use, for the first time, piezoelectric actuation. The generated stress from anchored piezoelectric films is employed to buckle a clamped-clamped beam to connect suspended source and drain terminals, while the residual stress in the beam is used to control the actuation voltage. This demonstration is the first of its kind to exploit residual stress to deliver a highly scalable switching mechanism that exhibits low actuation voltage ( \(\sim 1.8\) V), very fast switching ( \(\sim 80\) ns), and uniquely achieves an equivalent electric body bias via mechanical methods. Finite-element analysis and analytical simulations show a linear dependence of the switching voltage on the residual stress, while the voltage versus stress tuning slope is reduced linearly with scaling the piezoelectric film thickness (−16.6 mV/MPa for 10-nm thick aluminum nitride film). A scaling analysis shows that millivolt switching is possible for aggressively miniaturized relays, which highlights the great impact this technology could have on demonstrating ultralow power digital circuits and memories. [ABSTRACT FROM PUBLISHER]

An analytical model for the forming process of conductive-bridge resistive-switching random-access memory is developed. The measurable forming time can be calculated using this model giving the biasing condition and is verified to be correct through comparison with the experimental data. The forming time has been shown to have multiple-slopes in exponential dependence on the applied voltage, in agreement with measurement. The model is based on the identification of three steps in the forming process: 1) metal oxidation at the anode; 2) cation migration toward the cathode; and 3) backward filament growth due to electroplating from the cathode. The accuracy of the model has also been established via numerical simulation. [ABSTRACT FROM PUBLISHER]

This paper presents for the first time an RF nonlinearity analysis of complex multidevice radio frequency microelectromechanical system (RF MEMS) circuits. The IIP3 of different RF MEMS multidevice tunable-circuit concepts including digital MEMS varactor banks, MEMS switched capacitor banks, distributed MEMS phase shifters, and MEMS tunable filters, is investigated. Closed-form analytical formulas for the IIP3 of MEMS multidevice circuit concepts are derived. A nonlinearity analysis, based on measured device parameters, is presented for exemplary circuits of the different concepts using a multidevice nonlinear electromechanical circuit model implemented in Agilent Advanced Design System. The results of the nonlinear electromechanical model are also compared with the calculated IIP3 using derived equations for the digital MEMS varactor bank and MEMS switched capacitor bank. The degradation of the overall circuit linearity with increasing number of device stages is also investigated, with the conclusion that the overall circuit IIP3 is reduced by half when doubling the number of stages, if proper design precautions are not taken. Design rules are presented so that the mechanical parameters and thus the IIP3 of the individual device stages can be optimized to achieve a higher overall IIP3 for the whole circuit. In addition, the nonlinearity of a novel MEMS tunable capacitor concept introduced by the authors, based on an MEMS actuator with discrete tuning steps, is discussed and the IIP3 is calculated using derived analytical formulas. [ABSTRACT FROM PUBLISHER]

This paper demonstrates the efficacy of phase-change (PC) vias in reconfiguring RF front-end circuits for multiband/multi-standard operation. Constructed using two series-connected (SC) GeTe vias, a PC switch can be reversibly transformed between a high R{OFF} state and a low R{ON} state within 1 \mus. Using such PC switches to switch the inductor in a resonator, two LC voltage-controlled oscillators (VCOs) based on: 1) a SC and 2) a coupling-controlled (CC) resonator are developed. Designed and fabricated in 0.13-\mum CMOS in conjunction with an in-house GeTe process, the VCOs can switch their operating frequency over widely separated bands. Wide tuning ranges of 2.89–4.23/(4.93–7.79) and 4.80–8.53/(5.28–10.20) GHz were achieved in the off/on state for the SC/(CC) VCOs. The measured phase noise over the entire tuning range was lower than -103.4 and -102.7~dBc/Hz, at a 1-MHz offset frequency, respectively. [ABSTRACT FROM AUTHOR]

The electron–hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SSavg\sim 40~\rm mV/\rm dec up to VDD. Furthermore, it has been demonstrated that high on current levels (\sim40~\muA/\mum) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases. [ABSTRACT FROM AUTHOR]

We present analysis and modeling of a new innovative nanoelectromechanical switch (NEMS) with virtually zero leakage current, 1–3-V operation voltage, 1–10-ns switching time, and small footprint. In addition to acting as a simple switch, the physical structure of NEMS enables positioning of multiple contacts to realize functional logic gates in a single device. The implementation of basic two (or more) input logic gates using a single device improves reliability and reduces charging delay time. The reduction in the number of devices also improves yield and power while simplifying implementation. To evaluate NEMS design, we present an accurate NEMS SPICE circuit simulation model which enables the measurement of NEMS timing and power requirement. Based on the model and the device fabrication data, we show that NEMS ISCAS-85 circuit shows significant improvement over CMOS technology counterpart (using 65- and 45-nm technology). [ABSTRACT FROM AUTHOR]

Polarization engineering in 30-nm Pb (Zr,Ti) O3 (PZT)/AlGaN/GaN high-electron-mobility transistors (HEMTs) is demonstrated. The coupling between ferroelectric polarization and 2-D electron gas (2DEG) showed a remarkable increase in transconductance during the down-sweep process; this can be attributed to the switching of ferroelectric polarization. With the increase in maximum gate voltage, the transfer curve showed a positive shift; this is because of the increase in polarization charges induced by gate voltage. The drain electric field affected the polarization of ferroelectric layer, leading to different hysteresis behaviors and peak transconductance trends of transfer curves. To decrease the effect of drain electric field on gate, a small drain voltage was used to evaluate the characteristics of PZT/AlGaN/GaN. The variation in peak transconductance was used to estimate the recovery and pinning degree of polarization. The ferroelectric layer modulates the 2DEG in ferroelectric/AlGaN/GaN HEMTs; this mechanism provides guidelines for designing and electrically controlling ferroelectric/AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

Enlargement of memory window through forming compliance current was demonstrated in Gd:SiO2 resistive random access memory (RRAM) with a gadolinium (Gd) electrode. Lower forming compliance current for Gd:SiO2 RRAM with a Gd electrode results in larger memory window as compared with the RRAM with a Pt electrode. Through analyses on the current conduction mechanism, we demonstrate that a lower forming compliance current leads to a thinner conductive filament forming and less oxygen ions penetrating into Gd electrode, which caused higher on current and lower off current. Furthermore, a possible resistive switching model was proposed to explain the effect of Gd electrode on RRAM device. [ABSTRACT FROM AUTHOR]

Continuum phase-field simulations show how a multidomain ferroelectric capacitor in series with a resistor can exhibit a transient response in which the ferroelectric behaves as a negative capacitor. We show that accelerating domain growth leads to negative capacitance (NC), and this happens even when there is no initial switching of the domains. The observed behavior is in close agreement with experimental results of NC transients seen recently in a number of ferroelectric material systems. [ABSTRACT FROM AUTHOR]

Resistive-switching random access memory (RRAM) is widely considered as a disruptive technology. Despite tremendous efforts in theoretical modeling and physical analysis, details of how the conductive filament (CF) in metal-oxide-based filamentary RRAM devices is modified during normal device operations remain speculative, because direct experimental evidence at defect level has been missing. In this paper, a random-telegraph-signal-based defect-tracking technique (RDT) is developed for probing the location and movements of individual defects and their statistical spatial and energy characteristics in the CF of state-of-the-art hafnium-oxide RRAM devices. For the first time, the critical filament region of the CF is experimentally identified, which is located near, but not at, the bottom electrode with a length of nanometer scale. We demonstrate with the RDT technique that the modification of this key constriction region by defect movements can be observed and correlated with switching operation conditions, providing insight into the resistive switching mechanism. [ABSTRACT FROM PUBLISHER]