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The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

This paper describes the application of electrical circuit simulations in intelligent power module development for hybrid vehicles, electric vehicles, and fuel cell vehicles. The limitations of the conventional design and simulation systems are discussed, and efforts for overcoming these limitations are described. The introduction of a physics-based insulated-gate-bipolar-transistor model with a surface-potential MOSFET core into the design flow is described. Finally, future expectations for necessary simulation technology development are given. [ABSTRACT FROM PUBLISHER]

In this paper, the resistive switching behavior of a single-component-polymer resistive memory device based on polychloro-para-xylylene (parylene-C) is comprehensively studied. With the excellent chemical stability and high process compatibility of parylene-C, an 8 \times 8 crossbar array with a sandwiched structure of parylene-C and active electrodes is fabricated, which can be integrated in the CMOS back-end process and shows great potentials for future transparent, low-cost, flexible, and high-density nonvolatile memory applications. This organic memory device exhibits excellent performance with a \10^7 on/ off current ratio, nanosecond set/reset speed, and low switching voltages, as well as good retention and cycling endurance behaviors. The switching mechanism is systematically investigated with the comparison between active electrodes (Al, Cu, or Ag) and an inert electrode (Pt), as well as the dependence on temperature and device area. [ABSTRACT FROM AUTHOR]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the forming-free resistive-switching (RS) behavior in the \Ru/REOx/\TaN (\RE =\break \Ce, Pr, Sm, and Eu) memory device using \CeOx, \PrOx, \SmOx, and \EuOx thin films fabricated in a full-room-temperature process. The dominant conduction mechanism of \Ru/REOx\/ \TaN memory devices in the low-resistance state is ohmic behavior, whereas the high-resistance state is space-charge-limited conduction. The \Ru/CeOx \/\TaN devices show a high resistance ratio of > \10^4, reliable data retention for \10^5 \ \s, and stable endurance characteristics for up to 1000 cycles. This result suggests the high concentration of the cerium ions and the low density of chemical defects (oxygen vacancies) in the \CeOx film. The \Ru/CeOx\/\TaN structure memory is a very promising candidate for future nonvolatile RS memory applications. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM) devices based on storage layers, p-n junctions and transistors, such as FLASH, suffer from poor retention at high temperature, high voltage writing, and wear out while cycling. This paper presents the structure, operation, and modeling of a nanoelectromechanical NVM based on the switching of a free electrode between two stable states. This electrode, called the shuttle, has no mechanical anchors and commutes between two positions. It is guided inside an insulator pod. Adhesion forces between the shuttle and fixed electrodes serve to hold the shuttle in stable positions. Smooth metal layers give strong Van der Waals stiction between two surfaces in contact. Memory detection is obtained by probing the conductance between two fixed contacts; the shuttle serves as a switchable open/short electrode. Electromechanical contacts have an ideally large resistance ratio between on and off levels. At microscale, gravity is found to be negligible compared with adhesion forces, which motivates the anchorless design for high-temperature data storage. The model proposed is based on charge induction over the surface of metal electrodes and is validated by finite-element method. Kinematic equations and energy transfers of the shuttle device are explored. Due to its unique anchorless design, the scalability of the anchorless shuttle memory is found to be excellent. [ABSTRACT FROM AUTHOR]

This paper estimates the temperature distribution within a spin-torque-transfer RAM (STTRAM) cell due to self-heating using a thermal simulation based on the finite volume method. The analysis shows that, due to high switching current and small volume of the magnetic tunnel junction (MTJ), there can be significant rise in temperature in the MTJ as well as the silicon transistor. The impacts of the increased temperature on operational reliability metrics of the STTRAM cell, i.e., read disturb, write failure, and sensing accuracy, are evaluated. It is shown that, due to the self-heating effect, the operational reliability of an STTRAM cell depends on the read–write history of that cell. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/\2)(Seff/Soff) - \0.56(Son/Soff) - \0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology. [ABSTRACT FROM AUTHOR]

High leakage power in sub-100-nm memory technology nodes drives the need for nonvolatile memory devices to reduce power consumption and enhance battery life. Spin-transfer torque magnetic tunneling junction (STT-MTJ) is a promising nonvolatile memory device with comparable read and write performances as SRAM and eDRAM with almost zero standby power. In this paper, we present a simulation framework that can solve transport [using nonequilibrium Green's function (NEGF) formalism] and magnet dynamics [using Landau–Lifshitz–Gilbert (LLG) equation] self-consistently to study the read and write performances of STT-MTJ. Due to process variations, thermal disturbances, and stray fields, the performance of STT-MTJ degrades and results in one transistor–one STT-MTJ (1T–1STTMTJ) memory failures. A thorough memory design space investigation can help us to reduce such failures. Hence, we present a design space exploration framework for 1T–1STTMTJ memory, which consists of magnetic materials with different RAPA products, different genres of MTJ stacks, and a transistor. A comprehensive study based on critical memory performance metrics such as tunneling magnetoresistance, JC, and write cycle shows the relative merits and demerits of each MTJ stack for embedded memory applications. Finally, the benefits of synthetic antiferromagnet free layer in providing immunity against stray fields are shown illustrating the need for coupled free-layer stacks in scaled technology nodes. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, the study of the application of a lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-\mu\m LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. [ABSTRACT FROM AUTHOR]

The GaN high-electron mobility transistor (HEMT) structure has been widely investigated, particularly for radio-frequency applications. This structure is suitable for high-frequency switching applications in power electronics because of the high breakdown field of GaN and the high mobility of the channel. In this paper, a physical model for predicting the power-switching operation of GaN-based HEMTs as a function of material and device parameters is proposed. Analytical equations for total losses and power dissipation density are derived and discussed both qualitatively and quantitatively. [ABSTRACT FROM PUBLISHER]

This paper reports the effects of rapid thermal annealing (RTA) on resistive switching (RS) characteristics and mechanisms of \SrZrO3 (SZO)-based memory devices. SZO thin films were deposited on \LaNiO3 (LNO) (\100)/\Pt/Ti/SiO2/\Si using radio-frequency magnetron sputtering and were followed by an RTA process in \N2, Ar, and \O2 ambients, respectively, at various temperatures for improving RS performance. Experimental results indicate that an SZO device annealed in \O2 at 600 ^\circ\C (\O2-600) exhibits stable RS properties and has a high device yield (\sim 90%), a reliable retention characteristic (up to \1 \times \10^6\ \s at 100 ^\circ\C), and steady nondestructive readout properties (over \1.4 \times \10^4\ \s at 100 ^\circ\C). However, by increasing RTA temperature to more than 700 ^\circ\C, random formation of LNO (110) precipitates on the bottom surface of SZO grains might shorten the effective thickness of the SZO thin films. Furthermore, a strong electric field possibly occurs at the region between Al top electrodes and low-resistivity LNO precipitates. It is speculated that an RS phenomenon, which occurs within SZO grains instead of on grain boundaries, easily leads to RS failure, further resulting in severe degradation of device yield in the \O2-700 and \O2-800 devices. When compared with other devices, \O2-600 SZO memory devices exhibit highly reliable RS characteristics. [ABSTRACT FROM AUTHOR]

The aim of this paper is to demonstrate the application of the superjunction (SJ) design in an insulated gate bipolar transistor (IGBT). Bipolar conduction is present and enhanced at the cathode side of the device, while the p-pillars collect the plasma deep from the anode side, thus significantly enhancing its turn-off speed. The disconnected soft \punchthrough+\ (\SPT+) SJ IGBT is similar to the SJ IGBT, which we have previously reported, but the drift region pillars do not extend up to the cathode contact. Instead, the upper part of this device is similar to the \SPT+ IGBT, i.e., it features an \n+ injector around the p-well and the n-drift region that is lightly doped. The improvement in the overall performance is impressive (25% lower on-state losses and 30% lower switching losses) and can indeed justify the technology cost associated with the SJ technology. We also demonstrate how this technology can be used to form a snapback-free reverse conducting IGBT. [ABSTRACT FROM PUBLISHER]

In this paper, we examine the performance characteristics of bilayer graphene pseudospin devices as we scale the layer width of the monolayers of graphene which comprise the bilayer structure. We find that, for layer widths of 30 nm, the device performance can exceed analytical predictions due to thermal smoothing of the interlayer interactions. However, when the device is further scaled to 20 nm and below, we find an appreciable drop of the maximum current the device can sustain when compared with the predicted values which result from increased quantum interference between injected quasi-particles and those reflected off of the excitonic gap opened at the Fermi energy. These results provide important insight into the maximum achievable performance characteristics and optimal device-design parameters for this promising potential post-CMOS logic device. [ABSTRACT FROM PUBLISHER]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

An overview on the history of the development of insulated gate bipolar transistors (IGBTs) as one key component in today’s power electronic systems is given; the state-of-the-art device concepts are explained as well as an detailed outlook about ongoing and foreseeable development steps is shown. All these measures will result on the one hand in ongoing power density and efficiency increase as important contributors for worldwide energy saving and environmental protection efforts. On the other hand, the exciting competition of more maturing Si IGBT technology with the wide bandgap successors of GaN and SiC switches will go on. [ABSTRACT FROM AUTHOR]

Hyper-FET, an emerging device with unconventional characteristics, exhibits sub-kT/q switching and can attain higher ON current ( I \mathrm{\scriptscriptstyle ON} ) than standard FinFETs with matched OFF current ( I \mathrm{\scriptscriptstyle OFF} ). In continuation to the insights on the device level design methodology conveyed in part I [1], here we analyze the circuit implications of the unique characteristics of Hyper-FETs, such as hysteresis and abrupt switching. We provide a comprehensive discussion on the design of Hyper-FET-based circuit primitives, such as inverter, NOR and NAND gates. We emphasize on tailoring the hysteresis to avoid functional failure in logic circuits and deduce the correspondence between hysteresis observed in the device and circuit characteristics. To complement the device level constraints presented in part I, here we present additional stringencies for material parameters to aid in designing Hyper-FET-based logic gates with regenerative property and rail-to-railswing. Our analysis indicates that, at low V\sf DD (<0.3 V), properly designed Hyper-FET-based inverters can exhibit 25%–68% less energy at iso-delay (compared with FinFET-based CMOS inverters). We also provide targets for future material exploration. [ABSTRACT FROM AUTHOR]

Although Marx-bank connection of avalanche transistors is widely used in applications requiring high-voltage nanosecond and subnanosecond pulses, the physical mechanisms responsible for the voltage-ramp-initiated switching of a single transistor in the Marx chain remain unclear. It is shown here by detailed comparison of experiments with physical modeling that picosecond switching determined by double avalanche injection in the collector–base diode gives way to formation and shrinkage of the collector field domain typical of avalanche transistors under the second breakdown. The latter regime, characterized by a lower residual voltage, becomes possible despite a short-connected emitter and base, thanks to the 2-D effects. [ABSTRACT FROM PUBLISHER]

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation). [ABSTRACT FROM PUBLISHER]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

A highly tunable oscillator using magnetic tunnel junctions (MTJs) has been developed through integration with CMOS ring oscillators. MTJs are used to replace the pMOS transistors in a typical CMOS inverter fabricated in 40-nm CMOS. The hybrid MTJ-CMOS devices exhibit a voltage-controlled oscillator gain of 300–500 MHz/V and are tunable with respect to both voltage and magnetic field. [ABSTRACT FROM AUTHOR]

We investigate in detail the effects of metal electrodes on the switching performance and conductive filament (CF) stability of HfO2-based RRAM. The current–voltage characteristics of the devices exhibit different electrode-dependent RESET profiles which we attempt to clarify. With the insight from the experimental data, we employ first-principles calculations to have a better microscopic understanding of the devices. We study the charge injection, formation of Frenkel pairs, and diffusion of oxygen defects (oxygen vacancies Vo and oxygen interstitials Oi) that are important in the CF creation and stability during the device operation. Since the presence of Ti in RRAM has been associated with the creation of substoichiometric TiOy region at the Ti/HfO2 interface, we also explore different Ti and Hf suboxides to understand the possible composition of that interface. Our calculations suggest that the composition of the interface would be Ti2O/Hf2O3 from thermodynamic perspective. By combining the experimental and calculations results, we show that the concentration of oxygen interstitial (Oi) ions in the oxide after CF formation is larger for RRAM devices with inert electrodes (like Pt) compared with O reactive electrodes (like Ti) which results in degraded device performance. The lower Oi concentration in HfO2 layer with Ti electrodes results in improved CF thermal stability and device variability. [ABSTRACT FROM AUTHOR]

Research on memory devices is a highly active field, and many new technologies are being constantly developed. However, characterizing them and understanding how to bias for optimal performance are becoming an increasingly tight bottleneck. Here, we propose a novel technique for extracting biasing parameters, conducive to desirable switching behavior in a highly automated manner, thereby shortening the process development cycles. The principle of operation is based on: 1) applying variable amplitude, pulse-mode stimulation on a test device in order to induce switching multiple times; 2) collecting the data on how pulsing parameters affect the device’s resistive state; and 3) choosing the most suitable biasing parameters for the application at hand. The utility of the proposed technique is validated on TiOx-based prototypes, where we demonstrate the successful extraction of biasing parameters that allow the operation of our devices both as multistate and binary resistive switches. [ABSTRACT FROM AUTHOR]

We report a 3-D-stackable 1S1R passive cross-point resistive random access memory (RRAM). The sneak (leakage) current challenge in the cross-point RRAM integration has been overcome utilizing a field-assisted superlinear threshold selector. The selector offers high selectivity of >10^7 , sharp switching slope of < 5 mV/decade, ability to tune the threshold voltage, stable operation at 125 °C, and endurance of >10^{11} . Furthermore, we demonstrate 1S1R integration in which the selector-subthreshold current is <10 pA while offering >10^2 memory ON/OFF ratio and >10^6 selectivity during cycling. Combined with self-current-controlled RRAM, the 1S1R enables high-density and high-performance memory applications. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

Carbon nanotube (CNT)-based random access memory (NRAM) cells are measured to investigate cell program at different set current compliances and temperatures. Then, a physical model is proposed to explain the mechanism of cell resistance switching. Specifically, the changes in the NRAM cell tunneling current and resistance can be attributed to the variation of the distance between CNTs. An attraction force ( F\mathrm {attraction}) , generated by electrical induction, reduces the distance, whereas a repulsion force ( F\mathrm {repulsion}) , generated by phonon-induced temperature, increases the distance. It is proposed that the dominance of these two forces is reversed during set and reset programs, possibly due to the reduction of F\mathrm {repulsion} in set program. Finally, two verify-reset schemes are proposed to improve the NRAM cell verify-program performance. The first proposal, multiple-pulse reset demonstrates 23% program time reduction by skipping a cell resistance read between two successive reset pulses. The second proposal, gate-pulse reset is calculated to decrease more than 40% program energy by reducing bitline charge energy in array program. [ABSTRACT FROM AUTHOR]

We introduce a new technique to study the crystallization process in phase-change memory. By this technique, crystallization is characterized in the ON-state at extremely low currents, allowing to extend the time scale of crystallization times to more than two decades. To describe the pulse-induced crystallization in the set regime, we develop a finite-element method model based on localized conduction in the amorphous phase and non-Arrhenius crystallization kinetics. The range of crystallization times is then extended to even lower currents in the subthreshold regime, where the model allows describing the crystallization kinetics thus providing the physics-based prediction of read disturb. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) devices are gathering momentum, with a number of recent market introductions for a wide range of applications such as point-of-load converters, OFF-line switching power supplies, battery chargers, and motor drives. This paper studies the basic characteristics of a 600 V cascode GaN switch, such as voltage distribution during the turn-ON and turn-OFF transition. The switching loss mechanism of the cascode GaN switch is analyzed in detail, including the impact of the package parasitic inductance in both hard- and soft-switching modes. A soft-switching 5 MHz boost converter is developed and shows the advantages and the potential of the cascode GaN. [ABSTRACT FROM AUTHOR]

Based on the band diagram analysis and systematic measurements, comprehensive description of the output characteristics of tunnel FETs (TFETs) operation is proposed. We show that both tunneling junctions have to be considered simultaneously to explain TFET behavior correctly. For the first time, we present and investigate in detail untruncated ID(VD) measurements of TFETs. We prove that competition between the two tunneling junctions explains these experiments. Insights on the links between ID(VG) and ID(VD) curves are provided, which reveal the origin of the tunneling current in the device. Our theory also enables to clarify previously reported ID(VD) results. [ABSTRACT FROM AUTHOR]

A new wireless 3-D integrated circuit connection method, magnetic-sensing transmission interface (MTI), is reported for the first time. Signal transmission through the MTI implemented by placing a high-sensitivity sensor with perpendicular magnetic anisotropy on the top of a microcoil transmitter is successfully demonstrated. This new contactless magnetic signal transmission method featuring low-power, wide-bandwidth, and multilayer wireless data transmission is a viable candidate for future 3-D circuit integration technology. [ABSTRACT FROM AUTHOR]

We report on the fabrication of organic electrochemical transistors structured by nanoimprint lithography. The devices were scaled down as a result of our previous findings for inkjet printed transistors, where a reduced source-drain width and a shorter distance to the gate resulted in higher ON-to-OFF current ratios. We could show that these findings also prove true for transistors with feature sizes below 10 \mum . Furthermore, we fabricated inverters and NAND gates with switching times below 1 s. These logic gates mark an important step for organic electrochemical transistors toward their usability in more complex logic circuits. [ABSTRACT FROM PUBLISHER]

The sub-threshold swing (S) defines the sharpness of ON-OFF switching of a field effect transistor (FET), with S=0 corresponding to abrupt switching characteristics. While thermodynamics dictate S\geq 60~mV/decade for classical FETs, a new class of switches which we call “Landau switches” e.g., suspended gate FET (SG-FET) and ferroelectric FET (FE-FET) use inherently unstable (negative capacitance) gate insulators to achieve abrupt switching. Unfortunately, S=0 switching in Landau switches is always achieved at the expense of an intrinsic hysteresis, making them unsuitable for low-power applications. The fundamental question therefore is: under what conditions, hysteresis-free abrupt switching can be achieved in a Landau switch? In this paper, we first provide an intuitive classification of all semiconductor FETs in terms of their energy landscapes and identify a two-well energy landscape as the characteristic feature of all Landau switches. We then use the SG-FET as an illustrative example to conclude that a flat energy landscape is essential for hysteresis-free abrupt switching. In contrast, a hysteresis-free smooth switching (S\leq 60~mV/decade) is less restrictive, and is obtained by stabilizing the unstable gate insulator in its negative capacitance regime. Our conclusions have broad implications for the analysis and design of ultralow power sub-60 mV/decade switches. [ABSTRACT FROM AUTHOR]

A laterally diffused metal–oxide–semiconductor transistor (LDMOST) with ultralow specific ON-resistance (Rsp) is studied. In the OFF-state, the split p-type gate is depleted to achieve charge compensation with the n-type drift region, allowing a high n-drift doping. In the ON-state, holes accumulate in the split p-gate because the gate voltage (VG) applied induces simultaneously electron accumulation in the n-type drift region, enabling the on-current density to be not limited by the drift doping concentration and resulting in an ultralow value of Rsp. Moreover, the accumulated hole charges are stored in a capacitor during the turn-off process and are restored during the turn-on process, without an increase of the effective gate charge (Qg). Simulation results show good agreement with the theory. A 600 V device has an Rsp of <50\% of the conventional double-RESURF LDMOST with the effective Qg being almost the same. [ABSTRACT FROM PUBLISHER]

The programming speed in a phase change memory (PCM) relies on the kinetics of crystallization in the pulsed regime. To predict the programming speed and retention of a PCM, a careful understanding and modeling of crystallization in the phase change material is essential. In this paper, we study crystallization kinetics directly in PCM devices. From thermal annealing and pulsed-set experiments, we extract the temperature dependence of the crystallization in a wide temperature range between 170^\circC and the melting point (about 620^\circC). Our results indicate two markedly different activation energies below/above 300^\circC, thus providing evidence for a non-Arrhenius crystallization kinetics in PCM. [ABSTRACT FROM PUBLISHER]

In this paper, we optimize the stack of a 90-nm CMOS-friendly W\backslashAl2O3\backslashCu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al2O3\backslashCu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400^\circC and, on the other, to obtain excellent memory performances. After optimization of the Al2O3 layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (10 ns) at low voltage (<3~V), and low-current (10 \muA), and multilevel operation. Finally, 10^6 cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125^\circC. [ABSTRACT FROM AUTHOR]

This paper presents a physical model for program and retention transients in ferroelectric (FE) and charge hybrid nonvolatile memory. A region-by-region statistical model for domain switching in polycrystalline FEs was incorporated with the tunneling current simulations to predict the memory window (\Delta VTH) evolution during program and retention operations. The simulations validated the two-step program mechanism experimentally observed in such memories: rapid initial domain switching on account of high fields in the FE layer followed by field enhancement in the tunneling dielectric which initiates electron injection into the storage nodes. Further, these simulations were shown to accurately account for individual \Delta VTH from the two additive memory mechanisms at all program times. The depolarization effect was shown to be dominant for \Delta VTH loss at short and moderate retention time scales (<100~s). This model was further used to provide realistic estimates in achieving dual speed program and the corresponding dual mode retention characteristics akin to a DRAM and flash hybrid operation. [ABSTRACT FROM AUTHOR]

Soft-switching techniques are very attractive and often mandatory requirements in medium-voltage and medium-frequency applications such as solid-state transformers. The effectiveness of these soft-switching techniques is tightly related to the dynamic behavior of the internal stored charge in the utilized semiconductor devices. For this reason, this paper analyzes the behavior of the internal charge dynamics in high-voltage (HV) semiconductors, giving a clear base to perform overall converter optimizations and to understand the previously proposed zero-current-switching techniques for insulated-gate bipolar-transistor (IGBT)-based resonant dual active bridges. From these previous approaches, the two main concepts that allow switching loss reduction in HV semiconductors are identified: 1) shaping of the conducted current in order to achieve a high recombination time in the previously conducting semiconductors; and 2) achieving zero-voltage-switching (ZVS) in the turning-on device. The means to implement these techniques in a triangular-current-mode dual-active-bridge converter, together with the benefits of the proposed approaches, are analyzed and experimentally verified with a 1.7-kV IGBT-based neutral-point-clamped (NPC) bridge. Additionally, the impact of the modified currents in the converter's performance is quantified in order to determine the benefits of the introduced concepts in the overall converter. [ABSTRACT FROM PUBLISHER]

Resistive-switching random access memory (RRAM) devices utilizing a crossbar architecture represent a promising alternative for Flash replacement in high-density data storage applications. However, RRAM crossbar arrays require the adoption of diodelike select devices with high on–off -current ratio and with sufficient endurance. To avoid the use of select devices, one should develop passive arrays where the nonlinear characteristic of the RRAM device itself provides self-selection during read and write. This paper discusses the complementary switching (CS) in hafnium oxide RRAM, where the logic bit can be encoded in two high-resistance levels, thus being immune from leakage currents and related sneak-through effects in the crossbar array. The CS physical mechanism is described through simulation results by an ion-migration model for bipolar switching. Results from pulsed-regime characterization are shown, demonstrating that CS can be operated at least in the 10-ns time scale. The minimization of the reset current is finally discussed. [ABSTRACT FROM AUTHOR]

In this paper, we study the effect of highly doped n^+/p^+ Si as the bottom electrode on unipolar RRAM with Ni-electrode/\HfOx structure. With heavily doped p^+-Si as the bottom electrode, RRAM devices illustrate the coexistence of the bipolar and the unipolar resistive switching. Meanwhile, by substituting heavily doped n^+-Si, the switching behavior changes to that of the self-rectifying unipolar device. The asymmetry and rectifying reproducible behavior in a n^+-\Si/HfOx/\Ni device resulted from the Schottky barrier of defect states in the \SiOx/\HfOx junction and n^+ Si substrate, but this behavior is not seen for the p^+-Si bottom electrode case. With rectifying characteristics and high forward current density observed in the \Ni/HfOx/\n^{+}\Si device, the sneak current path in the conventional crossbar architecture was significantly suppressed. We believe that the proposed structure is a promising candidate for future crossbar-type RRAM applications. [ABSTRACT FROM AUTHOR]

The amorphous phase of the chalcogenide material in phase-change memory (PCM) devices is sensitive to temperature-activated crystallization and structural relaxation (SR). The latter leads to a change of device/material properties, such as the mobility band gap, the resistance, and the threshold voltage VT for threshold switching. In this paper, we present a VT drift model based on physical descriptions of the electrical transport, the threshold switching, and the SR. We introduce an analytical formula describing the relation between the drift slopes of resistance and VT via the subthreshold slope STS of the I– V curve. A numerical model predicting the time evolution of VT for different programmed states in the PCM multilevel cell is finally presented and compared with experiments. [ABSTRACT FROM PUBLISHER]

This paper investigates the multilevel behavior of phase-change random access memory devices with a dual phase-change material (PCM) stack, i.e., two PCMs stacked on one another. The dual PCM stack comprises of a \Ge2\Sb2\Te5 (GST) layer and a top PCM layer sandwiching a SiN barrier layer. The top PCM layer was varied in three different splits: \Ag0.5\In0.5\Sb3\Te6 (AIST), \Ge1\Sb4\Te7 (GST147), and nitrogen-doped GST (NGST). Extensive electrical characterization and statistical analysis were performed. The intrinsic properties of AIST, GST147, and NGST were used to explain the differences in electrical performances of the three multilevel device splits. The AIST/SiN/GST device split was found to have had the best electrical performance. The difference in electrical resistivities and thermal conductivities played a major role in the power consumption as well as the resistance values of the three multilevel states in these dual PCM multilevel devices. [ABSTRACT FROM PUBLISHER]

Understanding the physical mechanisms for resistance change in metal oxides is a key challenge to assess the scalability of resistive-switching random access memory (RRAM) devices. From this standpoint, the time dependence of filament formation and dissolution in metal oxides can provide a useful insight into the fundamental mechanism of resistive switching. In this paper, we show an experimental study of the time-dependent filament growth and of the voltage dependence of set/reset times in \HfOx-based RRAM devices. The voltage across the device is shown to be regulated at any given time irrespective of the compliance current and the applied voltage, evidencing that voltage is the controlling parameter for the filament formation and dissolution during switching. These results are explained in terms of a thermally-activated ion migration model for filamentary switching. The model allows for an analytical calculation of the scaling dependence of set/reset times and energies in RRAM. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is \9\ \mu\m \times \425\ \mu\m. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-\mu \m CMOS process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively. [ABSTRACT FROM PUBLISHER]

A nonvolatile and programmable routing switch featuring two-varistor selected complementary atom switch (2V-1CAS also known as via-switch) is evaluated. The a-Si/SiN/a-Si varistor as a selector for the atom switch shows superior nonlinear current–voltage characteristics with high selectivity of ~105, which originates from the staircase barrier height in the layers. The two control lines connected to the varistors realize multiple fan-outs of the crossbar switch without select transistors. The $50\,\,\sf \times20$ crossbar switch block is demonstrated, where the atom switch is placed at each cross point and programmed through the varistors. The developed via-switch crossbar switch is a strong candidate for achieving energy-efficient nonvolatile field-programmable gate array in the Internet-of-Things applications. [ABSTRACT FROM AUTHOR]

In this brief, for the first time, an Euler–Lagrange equation oriented solution for minimizing the operation energy of state-of-the-art spin-transfer-torque magnetoresistance random access memory (STT-MRAM) is proposed. Utilizing the derived analytical solvable Landau–Lifshitz–Gilbert (LLG) model and Euler–Lagrange equation, a calculable method for minimizing the dynamic energy of STT-MRAM is founded. Experimentally, a write energy reduction by 30% is demonstrated in the context of a certain write error rate. This brief provides a pragmatic method for achieving high energy-efficiency and reliable STT-MRAM operations. [ABSTRACT FROM AUTHOR]

Self-rectifying using a pure HfO2 layer with asymmetric structure was realized in Pt/HfO2/n+-Si resistive random access memory (RRAM). The device exhibits repeatable self-rectifying behavior with high rectifying ratio (>105). The electrostatic effect induced by the asymmetric structure of the HfO2 layer is responsible for the rectifying behavior. This kind of rectifying paves a new way for resolving the sneak current issue in RRAM arrays. [ABSTRACT FROM AUTHOR]

As compared with Si as the substrate, ferroelectric (FE) HfZrOx with orthorhombic phase on Si0.56Ge0.44 substrate was found to demonstrate improved FE characteristics. Through the incorporation of Ge into the silicon substrate, remanent polarization (${P}_{r}$) can be further enhanced by 58% magnitude to $15~\mu \text{C}$ /cm2. Moreover, devices on Si0.56Ge0.44 show significant reliability enhancement in terms of negligible ${P}_{r}$ degradation up to 107 cycles under ±4 MV/cm with 10-kHz bipolar stress and desirable retention up to 104 s arising from smaller imprint effect against time at 85°C. The major role of Ge introduction into the substrate is to suppress the formation of the interfacial layer (IL) between HfZrOx/substrate and further reinforce the quality of the IL. The suboxide IL of the enhanced quality can be explained by the fact that it is too thin to trap charges while less vulnerable to defect generation due to stronger bonding with fewer oxygen vacancies. The results suggest that as the technology advances from Si into SiGe platform, HfZrOx-based devices possess more reliable ferroelectricity for metal–FE–semiconductor (MFS) gate-stack for the next-generation FeFET. [ABSTRACT FROM AUTHOR]