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The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]