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We study the reduction in residual image in low-temperature poly-Si oxide (LTPO) thin-film transistor (TFT)-based flexible organic light-emitting diode (OLED) displays on polyimide (PI) substrate. Conventional voltage compensation circuit (seven TFTs plus one capacitor) is used with modification of driving and some switching TFTs. The measurement results on the threshold-voltage (${V}_{\text{TH}}$) shift and SPICE simulation data on the pixel circuits indicate that the residual image is due to the PI charging effect when a single-gate coplanar poly-Si TFT is used as driving one. It is shown here that adding a bottom electrode to the coplanar poly-Si driving TFT (D-TFT) eliminates the residual image by shielding the poly-Si active layer from the PI charging effect. [ABSTRACT FROM AUTHOR]

Here, we report the physical electro-thermal modeling of nanoscale Y2O3-based memristor devices. The simulation is carried out by the combined software package of COMSOL Multiphysics and MATLAB. The presented physical modeling is based on the minimization of free energy at an applied voltage. The simulated results exhibit a stable pinched hysteresis loop in resistive switching (RS) response in multiple switching cycles. The RS responses show low values of coefficient of variability (${C}_{V}$), i.e., 17.36% and 17.09% in SET and RESET voltages, respectively, during cycle-to-cycle variation. The impact of voltage ramp rate (${V}_{RR}$) on the device characteristics such as switching response and synaptic plasticity behavior of the device is investigated. The simulated outcomes significantly depict the impact of oxide layer thickness on the switching voltages in the nanoscale device. [ABSTRACT FROM AUTHOR]

Pulse-to-pulse variability (PPV) is a vital nonideal effect in analog resistive memory, particularly for online training in emerging computing paradigms. The reported PPVs usually show two seemingly contradictory properties: large PPV amplitude between neighboring write pulses but statistically stable switching curves. In this article, a new insight is proposed to unambiguously decouple PPV into two independent components: variability and curve fluctuation. Furthermore, a phenomenological modeling and parameter extraction method is proposed to capture this characteristic. The proposed model can facilitate the exploration of PPV impact on neural network accuracy for online training. [ABSTRACT FROM AUTHOR]

A deep understanding of the underlying resistive switching mechanism for the implementation of volatile memristive properties is regarded as of great importance for enhancing their performance. Along these lines, a 2-D dynamical model is introduced to interpret the whole memristive pattern within the bilayer configuration, as well as the crucial of the dense layer of the Pt nanoparticles (NPs) on the local thermal distribution. Moreover, the probabilistic leaky-integrate-and-fire (LIF) neuron properties were simulated by considering a simple $\textit {RC}$ circuit in order to perform Bayesian extrapolation within a spiking neural network. A classification application is consequently demonstrated by using the liver tumor dataset. The advantageous capabilities of the stochastic-based spike neural networks (SNNs) are highlighted in striking contrast with the conventional artificial neural networks (ANNs), as well as the deterministic-based SNNs, in terms of prediction accuracy and power consumption. [ABSTRACT FROM AUTHOR]

In several recent studies, the probabilistic nature of magnetic tunnel junction (MTJ) switching has been utilized rather than suppressed for proposals and demonstrations of specific or novel scenarios or applications, such as true random number generation, neural spike generation, stochastic computing (SC), and probabilistic spin logic. Among all schemes of operations for generating tunable random signals, dual-biasing is very simple but also robust against device variations. When an MTJ is connected to a voltage source with polarity encouraging parallel (P)-to-antiparallel (AP) switching by spin-transfer torque (STT), and under a static bias field that favors P-state, the MTJ can switch back and forth between two states randomly, due to the state-dependent modulation of current by the tunneling magnetoresistance (TMR) of the MTJ. In this work, we demonstrate bipolar random signal generation by connecting two MTJs in series with a voltage source. [ABSTRACT FROM AUTHOR]

In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n-channel ferroelectric field-effect transistors (nFeFETs) and pFeFETs. It is discovered that: 1) the degree of charge trapping depends on the substrate that nFeFETs exhibit significant electron trapping but negligible hole trapping during memory write while pFeFETs exhibit much less electron trapping but significant hole trapping when heavily stressed; 2) due to enhanced electric field in the interlayer and semiconductor, the like initial polarization states (i.e., initialized by a pulse of the same polarity as the write pulse) could exacerbate charge trapping induced by the write pulse; 3) electron trapping is fully recoverable while hole trapping shows a semi-permanent component which involves interface trap generation; and 4) less significant charge trapping in pFeFETs allows immediate read-after-write at normal operating conditions. [ABSTRACT FROM AUTHOR]

The nucleation-limited switching (NLS) model has been shown in the literature to explain successfully the dynamics of polarization switching of polycrystalline ferroelectric films (FE) in various experiments. However, because of its mathematical complexity, the NLS model has yet to be implemented correctly and efficiently in the simulation of actual, experimental circuits with complex driving waveforms. Here, we reformulate NLS as a generalized polarization rate equation that captures correctly the incubation time of nucleation and the intra- and inter-grain switching statistics of kinetics without any restrictions on waveform and switching time scales. This formulation forms the basis for efficient numerical finite-difference computation, which is verified in realistic circuit simulations of a number of experiments. [ABSTRACT FROM AUTHOR]

Flexible memristor is one of the most promising wearable devices for abundant data storage and processing. In this work, interface engineering by inserting the Al2O3 barrier layer is carried out to construct Pt/TiOx/Al2O3/Pt/indium tin oxide (ITO) flexible artificial synapse device. The memristor performance can be maintained even under 1000 times of bending without degradation, demonstrating its excellent mechanical property. With the Al2O3 diffusion barrier layer, the oxygen vacancies (${V}_{\text {o}}$) movement is slowed down for filaments formation and rupture, thus it boosts up the synaptic plasticity, including long-term potentiation/depression, paired-pulse facilitation (PPF), and spike-timing-dependent plasticity (STDP). Moreover, on the basis of the enhanced symmetry and linearity of conductance for Pt/TiOx/Al2O3/Pt/indium tin oxide (ITO) memristor, the neural network simulation for supervised learning presents an online learning pattern recognition, the accuracy can achieve to 91.15%. Overall, the Pt/TiOx/Al2O3/Pt/ITO memristor with excellent flexibility is a promising emulator for biological synapses, which could be beneficial to future flexible memristor-based neuromorphic computing. [ABSTRACT FROM AUTHOR]

Complementary resistive switching (CRS) arises when two bipolar-mode memristive devices are antiserially connected, forming a single functional structure. The combined effect of both memristors leads to the appearance of high (HRS) and low (LRS) resistance windows in the current–voltage (${I}$ – $V$) characteristic that finds application in fields such as neuromorphic computing and logic circuits. In this work, the electric behavior of HfO2-based CRS devices intentionally fabricated with a common central electrode is investigated both from experimental and modeling viewpoints. Experiments reveal that the maximum voltage applied to the structure allows tuning the amplitude of the resistance window following a self-balance dynamics. The origin of the abrupt (digital) and gradual (analog) transitions between the HRS and LRS states is elucidated through the inclusion of the snapback and snapforward effects in the switching dynamics. The ${I}$ – ${V}$ characteristics of the CRS devices are compact modeled with two opposite-biased memdiodes and simulated in LTSpice using an equivalent three-terminal subcircuit. It is shown that the proposed model is able to reproduce with a high degree of accuracy not only the observed CRS behavior for HfO2 but also the main features exhibited by devices with a wide variety of oxide/electrode materials. [ABSTRACT FROM AUTHOR]

A back-end-of-line compatible 400 °C thermally robust perpendicular spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) memory cell with a tunnel magnetoresistance ratio of 130% is demonstrated. It features an energy-efficient spin-transfer-torque-assisted field-free spin-orbit torque (SOT) switching and a novel interface-enhanced synthetic antiferromagnet (SAF). The optimal SAF with a Ru (9 Å) spacer sandwiched by Co/Pt multilayers has a high SAF coupling field of 2.8 kOe. The parallel magnetic coupling between the CoFeB-based reference layer and the bottom Co/Pt multilayer is enhanced by a magnet-coupling face-centered cubic textured Co/Pt (5 Å) multilayer buffer. The thermally induced Pt–Fe interdiffusion is effectively reduced by the W (3 Å) trilayers of texture-decoupling diffusion multibarrier. The Ta/ $\beta $ -W and TaN/ $\beta $ -W composite SOT channels are thick enough to be the etching stop and sustain 400 °C annealing without transforming to $\alpha $ -W. Using the harmonic Hall voltage measurement, the Ta/W and TaN/W channels exhibit the large effective spin Hall angle of approximately −0.21 and −0.27, respectively. Scaling magnetic tunnel junction (MTJ) down to 30 nm size can reduce the switching time due to single-domain switching based on the micromagnetic simulation. The damping constant of ~0.018 is obtained by the ferromagnetic resonance measurement. A bigger damping constant reduces the switching time as predicted by the calibrated simulation. [ABSTRACT FROM AUTHOR]

In this work, we present a four-transistor-two-resistor (4T2R) ternary content addressable memory (TCAM) bit cell based on the resistive memory (RRAM), comprising the conventional two-transistor-two-resistor (2T2R) cell with two additional comparison transistors. It can effectively amplify the match-line signal ratio (ML-ratio), lower the leakage current of the match cell (${I}_{{\mathrm {MATCH}}}$), and suppress the read disturbance. The proposed concept is silicon verified using the 180 nm CMOS technology with transition-metal-oxide (TMO) RRAM integrated at the back-end-of-line (BEOL). It achieves a considerable ML-ratio of 1860 and a low ${I}_{{\mathrm {MATCH}}}$ of 11.15 nA on average. In a typical search operation, it shows a negligible ML drop at the match case and a large ML swing range at the mismatch case. The SPICE simulation results further show it can support a long word-length (WDL) of 256 under a clock rate of 100 MHz for search operations, which demonstrates its promise for highly parallel nonvolatile TCAM. [ABSTRACT FROM AUTHOR]

Memristor is a promising device as a fundamental building block for future unconventional system architectures such as neuromorphic computing, reconfigurable logic, and multibit memories. Therefore, to facilitate circuit design using memristors, accurate and efficient models spanning a wide range of programming voltages and temperatures are required. In the first part of this series, we propose a behavioral model for temperature dependence of nonvolatile switching dynamics of TiOx memristors. We begin by describing pulsed resistance transients (PRTs) of the memristors and then we use a multistage methodology to establish bias and temperature dependence of the model parameters. The proposed model is then shown to accurately describe the PRT characteristics of Pt/TiOx/Au and Pt/TiOx/Pt memristors. [ABSTRACT FROM AUTHOR]

New technologies are continuously investigated to overcome the physical limitations of the downscaling process of microelectronic industry in order to perpetuate the miniaturization of devices as well as to enhance their capabilities. Memories are important components of almost any modern system. Applications, such as portable devices for which magnetic storage is not viable, prompt the search for universal memories that combine writing and retention capabilities. In this context, materials and structures that exhibit resistive switching are of utmost importance for the development of nonvolatile memories. In this context, graphene oxide has emerged as a promising resistive medium in metal-insulator–metal memory structures, because of the low cost and easy processing. Despite the controversy on the switching mechanism, graphene oxide-based memristors have also been proposed as self-selective memory elements. Nonlinearity is a fundamental characteristic of any memristor. In this work, we explore the occurrence of switching in graphene oxide, even when weak nonlinearities are observed. Metal-graphene oxide-metal structures were subjected to voltage cycling by applying triangular inputs and measuring the current. The nonlinearities were quantified by harmonic analysis, using total harmonic distortion as a figure of merit. An increasing nonlinear behavior is observed as the condition for switching is built up for increasing input amplitudes. This parameter allows an earlier identification of the set process. The harmonic analysis helps to discriminate the nonlinear perturbation to the linear response and allowing modeling of the current-voltage curve. [ABSTRACT FROM AUTHOR]

A phase-change memory (PCM) model for robust and efficient simulations of circuits including neuromorphic ones is reported in this work. The features of a hysteretic dynamic resistance in the voltage domain, and the incubation in the crystallization, are covered in the model. The Landau–Khalatnikov (LK)-type equation for ferroelectric is used to develop the PCM hysteresis module. A voltage-controlled relaxation oscillation is successfully simulated for the Ge2Sb2Te5 (GST) PCM. A technique of direct evaluation (DE) is then developed to reformulate the PCM model without any internal node. A significant enhancement of simulation efficiency is achieved compared with the traditional approach without sacrificing the accuracy. The functional correctness of the PCM device model and the acceleration effect in circuit simulations are verified. [ABSTRACT FROM AUTHOR]

This article presents a multilevel design for spin–orbit torque (SOT)-assisted spin-transfer torque (STT)-based 4-bit magnetic random access memory (MRAM). Multilevel cell (MLC) design is an effective solution to increase the storage capacity of MRAM. The conventional SOT-MRAMs enable an energy-efficient, fast, and reliable write operation. However, unlike STT-MRAM, these cells take more area and require two access transistors per cell. This poses significant challenges in the use of SOT-MRAMs for high-density memory applications. To address these issues, we propose an MLC that can store 4 bits and requires only three access transistors. The effective area per bit of the proposed cell is nearly 58% lower than that of the conventional 1-bit SOT-MRAM cell. The combined effect of SOT and STT has been incorporated to design SOT-STT-based MLC that enables more energy-efficient and faster write operation than the regular MLCs. The results show that SOT–STT-based 4-bit MLC is 52.9% and 40% more efficient in terms of latency and energy consumption, respectively, when compared to 3-bit SOT-/STT-based MLC. [ABSTRACT FROM AUTHOR]

Understanding the switching mechanism of the volatile resistive switching random access memory (RRAM) device is important to harness its characteristics and further enhance its performance. Accurate modeling of its dynamic behavior is also of deep value for its applications both as selector and as short-term memory synapse for future neuromorphic applications operating in temporal domain. In this work, we investigate the switching and retention (relaxation) processes of the Ag-based metallic filamentary volatile resistive switching devices. We find that the switching process can be modeled by the ionic drift under electric field, while the retention process can be modeled by the ionic diffusion along the filament surface driven by the gradient of surface atomic concentration. Through further theoretical analysis, we also find that the ionic drift and ionic diffusion can be unified within the general Einstein relation. To confirm this relation, we collect ionic mobility and diffusivity data from the literature using the switching and retention model. Finally, we show that the read voltage dependent retention time can be explained by the competition between the ionic drift and diffusion flux. [ABSTRACT FROM AUTHOR]

This article proposes a high-performance trench MOSFET with multiple stepped accumulation layer for conduction enhancement. In the proposed device, a multiple stepped split-gate (SG) is employed and self-biased to form a conductive accumulation layer, which greatly improves the performances of the device. Numerical simulation results show that the specific ON-resistance of the device is 56.41 $\text{m}\Omega \cdot $ mm2 with a breakdown voltage (BV) of ~145 V, which is reduced by 20.3% compared with the conventional trench SG MOSFET. Moreover, the reverse recovery time of the integrated Schottky diode of the proposed device is also reduced by 37.5%, since the multiple stepped accumulation layer can also enhance the conduction capability in the reverse conduction state. In addition, the average gate drive power consumption of the proposed device is reduced by more than 2% when the frequency ranges from 20 to 250 kHz in comparison with that of the conventional one. [ABSTRACT FROM AUTHOR]

In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length (${L}_{\mathrm {ch}}$) and channel thickness (${T}_{\mathrm {ch}}$) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing. [ABSTRACT FROM AUTHOR]

In the above article , we wish to add additional information and clarifications regarding the gates and circuits. [ABSTRACT FROM AUTHOR]