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This paper proposes a new dynamic behavior model for single-electron transistors (SETs). A comprehensive review of modeling techniques and previous models was carried out aiming to remark the originality of the new proposed technique. Once established that SET is a nonlinear system, five classes of nonlinear models were simulated and compared to each other. Characteristic SET curves obtained using Simulation of Nanostructures were used as benchmark. The mean squared error (mse) was used as metric, and the simulation time was computed for each model. Regarding these two criteria—least mse and least simulation time—the Hammerstein–Wiener model outperformed the others models. [ABSTRACT FROM AUTHOR]

Among the different types of bilayer tunneling field-effect transistors exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, the utilization of InAs/GaSb channels proves to be an appealing means to enhance ON-current levels. Ultrathin channel thicknesses make quantum confinement be the agent that closes the broken gap of the InAs/GaSb heterojunction leading to a staggered gap which blocks the tunneling current in the OFF state. In this paper, the gate leakage tunneling current is analyzed as one of the main critical processes degrading the performance of the proposed structure. Appropriate gate stacks of HfO2/Al2O3 combined with gate-to-drain underlaps are shown to effectively suppress this leakage tunneling, while at the same time, preserve an adequate electrostatic control over the channel. Simulation results for the most optimized configurations feature ON-state levels of up to $400\mu \text{A}/\mu \text{m}$ and subthreshold swings of $\approx 3$ mV/dec over more than 7 decades of current. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

The layout-induced cylindrical breakdown may occur as a result of the multifinger or circular layout-induced 3-D curvature effect resulting in the breakdown voltage reduction of the power device significantly. In this paper, by using effective doping concentration (EDC) concept, the inherent 3-D problem is simplified as a 1-D problem. Based on the EDC concept, a 1-D analytical model is presented to qualitatively and quantitatively explore the impact of curvature effect on the breakdown mechanism of SOI lateral double diffused MOS. The analytical solutions are found out to be consistent with the simulation results well obtained from MEDICI, a commercial technology computer-aided design tool. To the best of our knowledge, the proposed model is the first 1-D model which can accurately describe the 3-D curvature effect. [ABSTRACT FROM AUTHOR]

In this paper, we propose an accurate method to extract the free carrier mobility in field effect transistors. This derivation relies only on the drift-diffusion transport model without the need to predefine the gate-voltage-mobility dependence. This approach has been assessed with technology computer-aided design simulations, confirming its robustness even in the presence of short-channel effects. Exploiting the proposed model, free carrier mobility is obtained in a 28-nm commercial bulk CMOS process at room temperature. [ABSTRACT FROM AUTHOR]

In this paper, we report anomalous behavior of transconductance ( gm ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The gm characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the gm behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical gm behavior. The effect of oxide thickness ( T\text {ox} ) variation on gm is also studied, which demonstrates a deviation from the conventional gm behavior for halo implanted devices with thicker T\text {ox} . A computationally efficient SPICE model is proposed to model gm characteristics which shows excellent matching with the measured data. [ABSTRACT FROM PUBLISHER]

A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analyses, and the simulated results are consistent very well with those from device simulation and measurement, whereas the results by the traditional old model deviate substantially. Furthermore, the comprehensive optimization of the MTP cells is made feasible thanks to the new model, such as device size, high voltage ramp rate, and reliability prediction. As a result, this compact cell model will be very useful for the designers to evaluate and optimize a single-poly MTP cell. [ABSTRACT FROM AUTHOR]